diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 1084aa42ba..016c8a741a 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -239,6 +239,14 @@ config BOARD_GOOGLE_DIRKS select SOC_INTEL_TWINLAKE select SYSTEM_TYPE_MINIPC +config BOARD_GOOGLE_DIRKSON + select BOARD_GOOGLE_BASEBOARD_NISSA + select RT8168_GEN_ACPI_POWER_RESOURCE + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE + select SOC_INTEL_TWINLAKE + select SYSTEM_TYPE_MINIPC + config BOARD_GOOGLE_DOCHI select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_WIFI_SAR if CHROMEOS @@ -888,6 +896,7 @@ config DRIVER_TPM_I2C_BUS default 0x0 if BOARD_GOOGLE_CRAASKOV default 0x1 if BOARD_GOOGLE_CROTA default 0x0 if BOARD_GOOGLE_DIRKS + default 0x0 if BOARD_GOOGLE_DIRKSON default 0x1 if BOARD_GOOGLE_DOCHI default 0x0 if BOARD_GOOGLE_DOMIKA default 0x1 if BOARD_GOOGLE_FELWINTER @@ -978,6 +987,7 @@ config TPM_TIS_ACPI_INTERRUPT default 13 if BOARD_GOOGLE_CRAASKOV default 13 if BOARD_GOOGLE_CROTA default 13 if BOARD_GOOGLE_DIRKS + default 13 if BOARD_GOOGLE_DIRKSON default 13 if BOARD_GOOGLE_DOCHI default 13 if BOARD_GOOGLE_DOMIKA default 13 if BOARD_GOOGLE_FELWINTER @@ -1072,6 +1082,7 @@ config MAINBOARD_PART_NUMBER default "Craaskov" if BOARD_GOOGLE_CRAASKOV default "Crota" if BOARD_GOOGLE_CROTA default "Dirks" if BOARD_GOOGLE_DIRKS + default "Dirkson" if BOARD_GOOGLE_DIRKSON default "Dochi" if BOARD_GOOGLE_DOCHI default "Domika" if BOARD_GOOGLE_DOMIKA default "Felwinter" if BOARD_GOOGLE_FELWINTER @@ -1155,6 +1166,7 @@ config VARIANT_DIR default "craaskov" if BOARD_GOOGLE_CRAASKOV default "crota" if BOARD_GOOGLE_CROTA default "dirks" if BOARD_GOOGLE_DIRKS + default "dirkson" if BOARD_GOOGLE_DIRKSON default "dochi" if BOARD_GOOGLE_DOCHI default "yavilla" if BOARD_GOOGLE_DOMIKA default "felwinter" if BOARD_GOOGLE_FELWINTER diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index bce6d1c83f..de17056ae2 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -45,6 +45,9 @@ config BOARD_GOOGLE_CROTA config BOARD_GOOGLE_DIRKS bool "-> Dirks (Acer Chromebox Mini CXM2 (TWL))" +config BOARD_GOOGLE_DIRKSON + bool "-> Dirkson" + config BOARD_GOOGLE_DOCHI bool "-> Dochi (Acer Chromebook Plus Spin 514)" diff --git a/src/mainboard/google/brya/variants/dirkson/Makefile.mk b/src/mainboard/google/brya/variants/dirkson/Makefile.mk new file mode 100644 index 0000000000..bc39984d6c --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/Makefile.mk @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/dirkson/gpio.c b/src/mainboard/google/brya/variants/dirkson/gpio.c new file mode 100644 index 0000000000..a60615a865 --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/gpio.c @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage for dirkson */ +static const struct pad_config override_gpio_table[] = { + /* A11 : EN_SPK_PA ==> NC */ + PAD_NC(GPP_A11, NONE), + /* A14 : USB_OC1# ==> USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : USB_OC2# ==> USB_A2_OC_ODL */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : USB_OC3# ==> USB_A3_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : NC ==> HDMI1_HPD_SUB_ODL*/ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* B4 : LAN_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, PLTRST), + /* B16 : I2C5_SDA ==> NC */ + PAD_NC(GPP_B16, NONE), + /* B17 : I2C5_SCL ==> NC */ + PAD_NC(GPP_B17, NONE), + + /* C0 : SMBCLK ==> NC */ + PAD_NC(GPP_C0, NONE), + /* C1 : SMBDATA ==> NC */ + PAD_NC(GPP_C1, NONE), + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C6 : SML1CLK ==> NC */ + PAD_NC(GPP_C6, NONE), + /* C7 : SML1DATA ==> NC */ + PAD_NC(GPP_C7, NONE), + + /* D2 : PWM_PP3300_BUZZER */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D6 : SRCCLKREQ1# ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC(GPP_D16, NONE), + + /* E5 : [] ==> USB_A4_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E5, 1, DEEP), + /* E9 : USB_OC0# ==> USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E22 : DDPA_CTRLCLK ==> DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + /* E23 : DDPA_CTRLDATA ==> DDPA_CTRLDATA */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + + /* F13 : GSXSLOAD ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F14 : GSXDIN ==> LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, DEEP, EDGE_SINGLE), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC(GPP_F15, NONE), + + /* H6 : I2C1_SDA ==> NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : I2C1_SCL ==> NC */ + PAD_NC(GPP_H7, NONE), + /* H8 : CNV_MFUART2_RXD ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : CNV_MFUART2_TXD ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H12 : UART0_RTS# ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : UART0_CTS# ==> NC */ + PAD_NC(GPP_H13, NONE), + /* H15 : HDMI_SRC_DDC_SCL */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : HDMI_SRC_DDC_SDA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H21 : IMGCLKOUT2==> LAN_PE_ISOLATE_ODL */ + PAD_CFG_GPO(GPP_H21, 1, DEEP), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + + /* R4 : DMIC_CLK_A_0A ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : DMIC_DATA_0A ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : DMIC_CLK_A_1A ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : DMIC_DATA_1A ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S0 : I2S1_SCLK ==> NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : I2S1_SFRM ==> NC */ + PAD_NC(GPP_S1, NONE), + /* S2 : I2S1_TXD ==> NC */ + PAD_NC(GPP_S2, NONE), + + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ + /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), + /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), + /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), + /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), + /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* H21 : IMGCLKOUT2==> LAN_PE_ISOLATE_ODL */ + PAD_CFG_GPO(GPP_H21, 1, DEEP), + /* GPP_B4 : [] ==> LAN_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +static const struct pad_config romstage_gpio_table[] = { + + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), +}; + +const struct pad_config early_graphics_gpio_table[] = { + /* A18 : NC ==> HDMI2_HPD*/ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> EC_SOC_HDMI_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + + /* E14 : DDSP_HPDA ==> HDMI1_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + /* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* E22 : DDPA_CTRLCLK ==> DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + /* E23 : DDPA_CTRLDATA ==> DDPA_CTRLDATA */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + + /* H15 : HDMI_SRC_DDC_SCL */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : HDMI_SRC_DDC_SDA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_early_graphics_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_graphics_gpio_table); + return early_graphics_gpio_table; +} + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/dirkson/include/variant/ec.h b/src/mainboard/google/brya/variants/dirkson/include/variant/ec.h new file mode 100644 index 0000000000..469e75c834 --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/dirkson/include/variant/gpio.h b/src/mainboard/google/brya/variants/dirkson/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/dirkson/memory/Makefile.mk b/src/mainboard/google/brya/variants/dirkson/memory/Makefile.mk new file mode 100644 index 0000000000..7991e5f735 --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/memory/Makefile.mk @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/dirkson/memory/ src/mainboard/google/brya/variants/dirkson/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 0(0b0000) Parts = MT62F1G32D4DR-031 WT:B, H9JCNNNCP3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-5.hex # ID = 2(0b0010) Parts = K3LKLKL0EM-MGCN +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 3(0b0011) Parts = K3LKBKB0BM-MGCP +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 4(0b0100) Parts = K3KL8L80CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 5(0b0101) Parts = H58G56BK8BX068, H58G56CK8BX146 +SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 6(0b0110) Parts = K3KL9L90CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 7(0b0111) Parts = H58G66BK8BX067 diff --git a/src/mainboard/google/brya/variants/dirkson/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/dirkson/memory/dram_id.generated.txt new file mode 100644 index 0000000000..2a8769551c --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/memory/dram_id.generated.txt @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/dirkson/memory/ src/mainboard/google/brya/variants/dirkson/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT62F1G32D4DR-031 WT:B 0 (0000) +MT62F512M32D2DR-031 WT:B 1 (0001) +H9JCNNNBK3MLYR-N6E 1 (0001) +K3LKLKL0EM-MGCN 2 (0010) +K3LKBKB0BM-MGCP 3 (0011) +H9JCNNNCP3MLYR-N6E 0 (0000) +K3KL8L80CM-MGCT 4 (0100) +H58G56BK8BX068 5 (0101) +K3KL9L90CM-MGCT 6 (0110) +H58G66BK8BX067 7 (0111) +H58G56CK8BX146 5 (0101) diff --git a/src/mainboard/google/brya/variants/dirkson/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/dirkson/memory/mem_parts_used.txt new file mode 100644 index 0000000000..f2459f39fa --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/memory/mem_parts_used.txt @@ -0,0 +1,22 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +MT62F1G32D4DR-031 WT:B +MT62F512M32D2DR-031 WT:B +H9JCNNNBK3MLYR-N6E +K3LKLKL0EM-MGCN +K3LKBKB0BM-MGCP +H9JCNNNCP3MLYR-N6E +K3KL8L80CM-MGCT +H58G56BK8BX068 +K3KL9L90CM-MGCT +H58G66BK8BX067 +H58G56CK8BX146 diff --git a/src/mainboard/google/brya/variants/dirkson/overridetree.cb b/src/mainboard/google/brya/variants/dirkson/overridetree.cb new file mode 100644 index 0000000000..6a5d444f12 --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/overridetree.cb @@ -0,0 +1,406 @@ +fw_config + field WIFI_SAR_ID 0 0 + option ID_0 0 + option ID_1 1 + end + field WIFI_TYPE 1 2 + option WIFI_ALL 0 + option WIFI_CNVI 1 + option WIFI_PCIE 2 + end +end + +chip soc/intel/alderlake + + register "sagv" = "SaGv_Enabled" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "0x1" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + # This port is repurposed from Type-C to type-A port. + # Still declare it as Type-C port in order to set PortResetMessageEnable UPD. + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_A0 + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB2_A1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # USB2_A2 + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB2_A3 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A4 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A4 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0 + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0 + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + # Enable the Cnvi BT Audio Offload + register "cnvi_bt_audio_offload" = "1" + + # Disable eDP on DDI portA + register "ddi_portA_config" = "0" + + # Enable HPD and DDC for DDI port A + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C3 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[2].desc" = ""Ambient"" + + # TODO: below values are initial reference values only + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 5500, + .max_power = 6000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 200 + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 1, + .time_window_max = 1, + .granularity = 1000 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on + probe WIFI_TYPE WIFI_CNVI + probe WIFI_TYPE WIFI_ALL + end + end + end + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + device ref hda on + chip drivers/sof + register "jack_tplg" = "rt5682" + device generic 0 on end + end + end + device ref pcie_rp7 on + # Enable PCIE 7 using clk 3 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW2_14" # GPP_F14 + register "device_index" = "0" + register "enable_aspm_l1_2" = "1" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + end # RTL8111H Ethernet NIC + device ref pcie_rp11 on + # Enable wlan PCIe 11 using clk 2 + probe WIFI_TYPE WIFI_PCIE + probe WIFI_TYPE WIFI_ALL + register "pch_pcie_rp[PCH_RP(11)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW1_03" + register "add_acpi_dma_property" = "true" + use usb2_port8 as bluetooth_companion + device pci 00.0 on + probe WIFI_TYPE WIFI_PCIE + probe WIFI_TYPE WIFI_ALL + end + end + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" + register "srcclk_pin" = "2" + device generic 0 on + probe WIFI_TYPE WIFI_PCIE + probe WIFI_TYPE WIFI_ALL + end + end + end + device ref emmc on end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(2, 3))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(1, 3))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A4"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(2, 2))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on + probe WIFI_TYPE WIFI_PCIE + probe WIFI_TYPE WIFI_ALL + end + end + chip drivers/usb/acpi + register "desc" = ""CNVI Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on + probe WIFI_TYPE WIFI_CNVI + probe WIFI_TYPE WIFI_ALL + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(2, 3))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A2"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A3"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(1, 3))" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A4"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(2, 2))" + device ref usb3_port4 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/dirkson/ramstage.c b/src/mainboard/google/brya/variants/dirkson/ramstage.c new file mode 100644 index 0000000000..1a9013b993 --- /dev/null +++ b/src/mainboard/google/brya/variants/dirkson/ramstage.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + /*Enable Type C port1 convert to Type A*/ + params->EnableTcssCovTypeA[1] = 1; + /* PCH xchi port number for Type C port1 port mapping */ + params->MappingPchXhciUsbA[1] = 2; + +} + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DID_INTEL_ADL_N_ID_1, 7, 3000, 6000, 25000, 25000, 78000 }, + { PCI_DID_INTEL_ADL_N_ID_2, 6, 3000, 6000, 25000, 25000, 78000 }, + { PCI_DID_INTEL_ADL_N_ID_3, 6, 3000, 6000, 25000, 25000, 78000 }, +}; + +const struct system_power_limits sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DID_INTEL_ADL_N_ID_1, 7, 63 }, + { PCI_DID_INTEL_ADL_N_ID_2, 6, 63 }, + { PCI_DID_INTEL_ADL_N_ID_3, 6, 63 }, +}; + +/* + * Psys_pmax considerations. + * + * Given the hardware design in dirkson, the serial shunt resistor is 0.01ohm. + * The full scale of hardware PSYS signal 1.6v maps to system current 6.009A + * instead of real system power. The equation is shown below: + * PSYS = 1.6v ~= (0.01ohm x 6.009A) x 50 (INA213, gain 50V/V) x PR222/(PR222 + R3193) + * PR222/(PR222 + R3193) = 0.5325 = 36K / (36K + 31.6K) + * + * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping between system input + * current and the actual system power. Since there is no voltage information + * from PSYS, different voltage input would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax should be 15v x 6.009A = 90.135W + * For Type-C 20V, the Psys_pmax should be 20v x 6.009A = 120.18W + * For a barrel jack, the Psys_pmax should be 19v x 6.009A = 114.171W + * + * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading, + * and the Psys_pmax setting is 120W. Then IMVP9.1 can calculate the current system + * power = 120W * 5A / 6.009A = 100W, which is the actual system power. + */ +const struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 6009, + .bj_volts_mv = 19000, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); +}