diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c
index 377f529a08..c2566c5d5b 100644
--- a/src/soc/qualcomm/x1p42100/clock.c
+++ b/src/soc/qualcomm/x1p42100/clock.c
@@ -294,6 +294,26 @@ static u32 *usb_sec_cbcr[USB_SEC_CLK_COUNT] = {
 	[USB_SEC_SYS_NOC_USB_AXI_CBCR] = &gcc->gcc_sys_noc_usb_axi_cbcr,
 };
 
+static u32 *disp_gdsc[MAX_DISP_GDSC] = {
+	[DISP_CC_CORE_GDSC] = &disp_cc->mdss_core_gdscr,
+};
+
+static u32 *mdss_cbcr[MDSS_CLK_COUNT] = {
+	[GCC_DISP_AHB_CBCR] = &gcc->gcc_disp_ahb_cbcr,
+	[GCC_DISP_XO_CBCR] = &gcc->gcc_disp_xo_cbcr,
+	[GCC_DISP_HF_AXI_CBCR] = &gcc->gcc_disp_hf_axi_cbcr,
+	[DISP_CC_MDSS_AHB_CBCR] = &disp_cc->mdss_ahb_cbcr,
+	[DISP_CC_MDSS_MDP_CBCR] = &disp_cc->mdss_mdp_cbcr,
+	[DISP_CC_MDSS_VSYNC_CBCR] = &disp_cc->mdss_vsync_cbcr,
+	[DISP_CC_MDSS_RSCC_AHB_CBCR] = &disp_cc->mdss_rscc_ahb_cbcr,
+	[DISP_CC_MDSS_RSCC_VSYNC_CBCR] = &disp_cc->mdss_rscc_vsync_cbcr,
+	[DISP_CC_XO_CBCR] = &disp_cc->xo_cbcr,
+	[DISP_CC_MDSS_DPTX3_PIXEL0_CBCR] = &disp_cc->mdss_dptx3_pixel0_cbcr,
+	[DISP_CC_MDSS_DPTX3_LINK_CBCR] = &disp_cc->mdss_dptx3_link_cbcr,
+	[DISP_CC_MDSS_DPTX3_AUX_CBCR] = &disp_cc->mdss_dptx3_aux_cbcr,
+	[DISP_CC_MDSS_DPTX3_LINK_INTF_CBCR] = &disp_cc->mdss_dptx3_link_intf_cbcr,
+};
+
 static struct clock_freq_config pcie_core_cfg[] = {
 	{
 		.hz = 100 * MHz,
@@ -500,6 +520,14 @@ enum cb_err clock_enable_usb_gdsc(enum clk_usb_gdsc gdsc_type)
 	return enable_and_poll_gdsc_status(usb_gdsc[gdsc_type]);
 }
 
+enum cb_err clock_enable_disp_gdsc(enum clk_disp_gdsc gdsc_type)
+{
+	if (gdsc_type >= MAX_DISP_GDSC)
+		return CB_ERR;
+
+	return enable_and_poll_gdsc_status(disp_gdsc[gdsc_type]);
+}
+
 enum cb_err usb_clock_enable(enum clk_usb clk_type)
 {
 	if (clk_type >= USB_CLK_COUNT)
@@ -623,6 +651,45 @@ static enum cb_err pll_init_and_set(struct x1p42100_ncc0_clock *ncc0, u32 l_val)
 	return CB_SUCCESS;
 }
 
+enum cb_err disp_pll_init_and_set(struct x1p42100_disp_pll_clock *disp_pll, u32 l_val, u32 alpha_val)
+{
+	int ret;
+	struct alpha_pll_reg_val_config disp_pll_cfg = {0};
+
+	disp_pll_cfg.reg_l = &disp_pll->pll_l;
+	disp_pll_cfg.l_val = l_val;
+
+	disp_pll_cfg.reg_alpha = &disp_pll->pll_alpha;
+	disp_pll_cfg.alpha_val = alpha_val;
+
+	disp_pll_cfg.reg_user_ctl = &disp_pll->pll_user_ctl;
+	disp_pll_cfg.user_ctl_val = 0x1;
+
+	clock_configure_enable_gpll(&disp_pll_cfg, false, 0);
+
+	disp_pll_cfg.reg_mode = &disp_pll->pll_mode;
+	disp_pll_cfg.reg_opmode = &disp_pll->pll_opmode;
+	ret = lucidole_pll_enable(&disp_pll_cfg);
+	if (ret != CB_SUCCESS)
+		return CB_ERR;
+
+	return CB_SUCCESS;
+}
+
+enum cb_err mdss_clock_enable(enum clk_mdss clk_type)
+{
+	if (clk_type >= MDSS_CLK_COUNT)
+		return CB_ERR;
+
+	/* Enable clock */
+	return clock_enable(mdss_cbcr[clk_type]);
+}
+
+void enable_disp_clock_tcsr(void)
+{
+	write32(TCSR_GCC_EDP_CLKREF_EN_ADDR, 0x1);
+}
+
 static void speed_up_boot_cpu(void)
 {
 	/* 1363.2 MHz */
diff --git a/src/soc/qualcomm/x1p42100/display/disp.c b/src/soc/qualcomm/x1p42100/display/disp.c
index f09adab34f..f4a999ec80 100644
--- a/src/soc/qualcomm/x1p42100/display/disp.c
+++ b/src/soc/qualcomm/x1p42100/display/disp.c
@@ -4,12 +4,68 @@
 #include <console/console.h>
 #include <timer.h>
 #include <soc/addressmap.h>
+#include <soc/clock.h>
 #include <soc/cmd_db.h>
 #include <soc/rpmh.h>
 #include <soc/rpmh_bcm.h>
 #include <soc/rpmh_config.h>
 #include <soc/rpmh_regulator.h>
 
+static struct clock_freq_config disp_cc_mdss_ahb_cfg[] = {
+	{
+		.hz = SRC_XO_HZ,        /* 19.2MHz */
+		.src = SRC_XO_19_2MHZ_AHB,
+		.div = QCOM_CLOCK_DIV(1),
+	},
+	{
+		.hz = CLK_37_5MHZ,
+		.src = SRC_DISP_CC_PLL1_MAIN_AHB,
+		.div = QCOM_CLOCK_DIV(16),
+	},
+	{
+		.hz = CLK_75MHZ,
+		.src = SRC_DISP_CC_PLL1_MAIN_AHB,
+		.div = QCOM_CLOCK_DIV(8),
+	},
+};
+
+static struct clock_freq_config disp_cc_mdss_mdp_cfg[] = {
+	{
+		.hz = CLK_575MHZ,
+		.src = SRC_DISP_CC_PLL0_MAIN_MDP,
+		.div = QCOM_CLOCK_DIV(3),
+	},
+	{
+		.hz = CLK_400MHZ,
+		.src = SRC_DISP_CC_PLL1_MAIN_MDP,
+		.div = QCOM_CLOCK_DIV(1.5),
+	},
+};
+
+void enable_mdss_clk(void)
+{
+	/*
+	 * Display clock initialization sequence
+	 * 1. Enable GCC clocks (AHB, AXI) - GCC clocks that are required for display
+	 * 2. Enable GDSC (power domain) - powers up the display subsystem
+	 * 3. Initialize display PLLs - required to use clock sources from disp_cc domain
+	 * 4. Configure and enable disp_cc clocks - enable display clocks
+	 */
+	mdss_clock_enable(GCC_DISP_AHB_CBCR);
+	clock_enable_disp_gdsc(DISP_CC_CORE_GDSC);
+	mdss_clock_enable(GCC_DISP_HF_AXI_CBCR);
+	disp_pll_init_and_set(apss_disp_pll0, L_VAL_1725MHz, DISP_PLL0_ALPHA_VAL);
+	disp_pll_init_and_set(apss_disp_pll1, L_VAL_600MHz, DISP_PLL1_ALPHA_VAL);
+	clock_configure(&disp_cc->mdss_ahb_rcg,
+		disp_cc_mdss_ahb_cfg, CLK_75MHZ, ARRAY_SIZE(disp_cc_mdss_ahb_cfg));
+	mdss_clock_enable(DISP_CC_MDSS_AHB_CBCR);
+	clock_configure(&disp_cc->mdss_mdp_rcg,
+		disp_cc_mdss_mdp_cfg, CLK_575MHZ, ARRAY_SIZE(disp_cc_mdss_mdp_cfg));
+	mdss_clock_enable(DISP_CC_MDSS_MDP_CBCR);
+	mdss_clock_enable(DISP_CC_MDSS_VSYNC_CBCR);
+	enable_disp_clock_tcsr();
+}
+
 /**
  * display_rpmh_init() - Initialize RPMh for display power management
  *
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index da082f66bd..73378ce59e 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -16,6 +16,7 @@
 #define CLK_400MHZ		(400 * MHz)
 #define CLK_75MHZ		(75 * MHz)
 #define CLK_575MHZ		(575 * MHz)
+#define CLK_37_5MHZ		(37.5 * MHz)
 
 /* CPU PLL*/
 #define L_VAL_1363P2MHz		0x47
@@ -745,14 +746,20 @@ void clock_enable_qup(int qup);
 void clock_configure_dfsr(int qup);
 void clock_configure_pcie(void);
 void clock_configure_usb(void);
+void enable_disp_clock_tcsr(void);
+void enable_mdss_clk(void);
 enum cb_err clock_enable_gdsc(enum clk_gdsc gdsc_type);
 enum cb_err clock_enable_pcie(enum clk_pcie clk_type);
 enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type);
 enum cb_err usb_clock_configure_mux(enum clk_pipe_usb clk_type, u32 src_type);
 enum cb_err usb_clock_enable(enum clk_usb clk_type);
 enum cb_err clock_enable_usb_gdsc(enum clk_usb_gdsc gdsc_type);
+enum cb_err clock_enable_disp_gdsc(enum clk_disp_gdsc gdsc_type);
 enum cb_err usb_prim_clock_enable(enum clk_usb_prim clk_type);
 enum cb_err usb_sec_clock_enable(enum clk_usb_sec clk_type);
+enum cb_err mdss_clock_enable(enum clk_mdss clk_type);
+enum cb_err disp_pll_init_and_set(struct x1p42100_disp_pll_clock *disp_pll,
+		u32 l_val, u32 alpha_val);
 void clock_configure_dfsr_table_x1p42100(int qup, struct clock_freq_config *clk_cfg,
 		uint32_t num_perfs);