From e1e658ad292f0cf4a810097b9eb5caaa62e1e404 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Fri, 17 Jun 2016 11:04:37 +0300
Subject: [PATCH] UPSTREAM: intel: Fix romstage main() with asmlinkage

Backport from haswell.

Change-Id: I585639f8af47bd1d8c606789ca026c6d2d0cc785
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15225
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
(cherry-picked from commit e325b223a2c48d35dedce1c20d055c23b0ea4bea)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354188
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
---
 src/cpu/intel/car/romstage.c     | 7 +++++++
 src/include/cpu/intel/romstage.h | 5 +++++
 2 files changed, 12 insertions(+)
 create mode 100644 src/cpu/intel/car/romstage.c

diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
new file mode 100644
index 0000000000..c6df446c6a
--- /dev/null
+++ b/src/cpu/intel/car/romstage.c
@@ -0,0 +1,7 @@
+#include <cpu/intel/romstage.h>
+
+void * asmlinkage romstage_main(unsigned long bist)
+{
+	mainboard_romstage_entry(bist);
+	return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h
index 0ebb91266b..c294c2edc0 100644
--- a/src/include/cpu/intel/romstage.h
+++ b/src/include/cpu/intel/romstage.h
@@ -1,7 +1,12 @@
 #ifndef _CPU_INTEL_ROMSTAGE_H
 #define _CPU_INTEL_ROMSTAGE_H
 
+#include <arch/cpu.h>
+
 /* std signature of entry-point to romstage.c */
 void main(unsigned long bist);
 
+void mainboard_romstage_entry(unsigned long bist);
+void * asmlinkage romstage_main(unsigned long bist);
+
 #endif /* _CPU_INTEL_ROMSTAGE_H */