Compile fixes from linuxBIOS hopefully it works for everyone again.

crt0.base
     - SMP compile fixes
     - No longer unconditionally include cpu/p5/start32.inc
         (it's been renamed  cpu/i386/entry16.inc)
ldscript.base
     - Simplfied, and moved some content into reset16.lds and entry16.lds
stddef.h
     - Use C style comments for #endif /* I386_STDDEF_H */
pirq_routing.h
     - The define is HAVE_PIRQ_TABLE not HAVE_PIRQ_ROUTING_TABLE
mtrr.c
     - Remove the need for defining INTEL_PPRO_MTRR
mainboard/xxx/Config
     - start32.inc is no longer automatically included include
       entry16.inc and reset16.inc where appropriate
       In particular if we are using a docipl we don't want
       reset16.inc or reset16.lds
tyan/guiness/mptable.c
     - Removed spurious define USE_ALL_CPUS
northbridge/intel/440gx/
     - Updated to compile with the factored generic memory code.
nortsouthbridge/sis/xxx/
     - Remove includes of northsouthbridge/sis/630/param.h did I add them?
       The file is gone now so including it is just bad...
NLBConfig.py
      - Allow relative filename arguments
      - Add directive ldscript to add an include file into
        our linker script
      - Fixed docipl to use strings when calling set_option
      - Allow target the target directive to use relative paths
      - Add extra dependencies to ldscript.lds

src/cpu/i386/entry16.inc

@@ -0,0 +1,137 @@
+/*
+This software and ancillary information (herein called SOFTWARE )
+called LinuxBIOS          is made available under the terms described
+here.  The SOFTWARE has been approved for release with associated
+LA-CC Number 00-34   .  Unless otherwise indicated, this SOFTWARE has
+been authored by an employee or employees of the University of
+California, operator of the Los Alamos National Laboratory under
+Contract No. W-7405-ENG-36 with the U.S. Department of Energy.  The
+U.S. Government has rights to use, reproduce, and distribute this
+SOFTWARE.  The public may copy, distribute, prepare derivative works
+and publicly display this SOFTWARE without charge, provided that this
+Notice and any statement of authorship are reproduced on all copies.
+Neither the Government nor the University makes any warranty, express
+or implied, or assumes any liability or responsibility for the use of
+this SOFTWARE.  If SOFTWARE is modified to produce derivative works,
+such modified SOFTWARE should be clearly marked, so as not to confuse
+it with the version available from LANL.
+ */
+/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
+ * rminnich@lanl.gov
+ */
+
+
+/** Start code to put an i386 or later processor into 32-bit 
+ * protected mode. 
+ */
+
+.text
+.code16
+.globl	EXT(_start)
+.type EXT(_start), @function
+
+/// We have a relative jump here to around the GDT. 
+EXT(_start): jmp _realstart
+/** This gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
+ * at 0x18; these are Linux-compatible. 
+ */
+
+/** GDT. we have modified this from the original freebios to make it 
+ * compatible with linux. This puts text at seg 0x10 and data at 0x18
+ */
+.globl EXT(gdtptr)
+EXT(gdtptr):
+	.word	4*8-1
+	.long	gdt		/* we know the offset */
+gdt:
+	.word	0x0000, 0x0000		/* dummy */
+	.byte	0x0, 0x0, 0x0, 0x0
+	
+	.word	0x0000, 0x0000		/* dummy */
+	.byte	0x0, 0x0, 0x0, 0x0
+	
+	.word	0xffff, 0x0000		/* flat code segment */
+	.byte	0x0, 0x9a, 0xcf, 0x0	
+	
+	.word	0xffff, 0x0000		/* flat data segment */
+	.byte	0x0, 0x92, 0xcf, 0x0	
+
+
+_realstart:
+	cli
+
+/* thanks to kmliu@sis.tw.com for this TBL fix ... */
+/**/
+/* IMMEDIATELY invalidate the translation lookaside buffer before executing*/
+/* any further code.  Even though paging is we, disabled could still get*/
+/*false address translations due to the TLB if we didn't invalidate it.*/
+/**/
+	xor	%eax, %eax
+	mov	%eax, %cr3    /* Invalidate TLB*/
+
+	/* invalidate the cache */
+	invd 
+
+	/* Note: gas handles memory addresses in 16 bit code very poorly.
+	 * In particular it doesn't appear to have a directive allowing you
+	 * associate a section or even an absolute offset with a segment register.
+	 *
+	 * This means that anything except cs:ip relative offsets are
+	 * a real pain in 16 bit mode.  And explains why it is almost
+	 * imposible to get gas to do lgdt correctly.
+	 *
+	 * One way to work around this is to have the linker do the
+	 * math instead of the assembler.  This solves the very
+	 * pratical problem of being able to write code that can
+	 * be relocated.
+	 *
+	 * An lgdt call before we have memory enabled cannot be 
+	 * position independent, as we cannot execute a call
+	 * instruction to get our current instruction pointer.
+	 * So while this code is relocateable it isn't arbitrarily
+	 * relocatable.
+	 *
+	 * In particular this code can be run with the base address of
+	 * the code segment at either 0xffff0000 or 0xf0000.
+	 * The first is what is initiallly loaded when the processor 
+	 * powers on.  The second is normal real mode segment 0xf000.
+	 *
+	 * At this point all the linker script does when calculating
+	 * gdtptr_offset is return the low 16 bits so your segment
+	 * must be 64K aligned.  So it wouldn't be too much work
+	 * to support other segments, I just don't see the point
+	 * right now.
+	 */
+	data32	lgdt %cs:EXT(gdtptr_offset)
+
+	movl	%cr0, %eax
+	andl	$0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
+	orl	$0x60000001, %eax /* CD, NW, PE = 1 */
+	movl	%eax, %cr0
+
+	/* Now that we are in protected mode jump to a 32 bit code segment. */
+	data32	ljmp	$0x10, $.Lprotected
+
+/*
+ *	When we come here we are in protected mode. We expand 
+ *	the stack and copies the data segment from ROM to the
+ *	memory.
+ *
+ *	After that, we call the chipset bootstrap routine that
+ *	does what is left of the chipset initialization. 
+ *
+ *	NOTE aligned to 4 so that we are sure that the prefetch
+ *	cache will be reloaded.
+ */
+	.align	4
+.Lprotected:
+	.code32
+	intel_chip_post_macro(0x10)	/* post 10 */
+
+	movw	$0x18, %ax
+	movw	%ax, %ds
+	movw	%ax, %es
+	movw	%ax, %ss
+	movw	%ax, %fs
+	movw	%ax, %gs
+

src/cpu/i386/entry16.lds

@@ -0,0 +1,2 @@
+	gdtptr_offset = gdtptr & 0xffff;
+	_start_offset = _start & 0xffff;

src/cpu/i386/entry32.inc

@@ -0,0 +1,5 @@
+	/* For starting linuxBIOS in protected mode */
+	.text
+	.align	4
+	.code32
+	intel_chip_post_macro(0x10)	/* post 10 */

src/cpu/i386/reset16.inc

@@ -0,0 +1,24 @@
+	.section ".text.reset_vector"
+	.code16
+.globl	EXT(reset_vector)
+EXT(reset_vector):
+#if _ROMBASE >= 0xffff0000
+	/* Hmm.
+	 * _start_offset is the low 16 bits of _start.
+	 * Theoretically we should have problems but it compiles
+	 * and links properly with binutils 2.9.5 & 2.10.90
+	 * This is probably a case that needs fixing in binutils.
+	 * And then we can just use _start.
+	 * We also need something like the assume directive in
+	 * other assemblers to tell it where the segment registers
+	 * are pointing in memory right now.
+	 */
+	jmp	EXT(_start_offset)
+#elif (_ROMBASE < 0x100000)
+	ljmp	$((_ROMBASE & 0xf0000)>>4),$EXT(_start_offset);
+#else
+#error	_ROMBASE is an unsupported value
+#endif
+
+	.text
+	.code32	

src/cpu/i386/reset16.lds

@@ -0,0 +1,17 @@
+/*
+ *      _ROMTOP                 : The top of the rom used where we
+ *				  need to put the reset vector.
+ */
+	_ROMTOP = (_ROMBASE >= 0xffff0000)? 0xfffffff0 : 0xffff0;
+
+SECTIONS {
+	. = _ROMTOP;
+	.text.reset_vector (.): {
+		*(.text.reset_vector)
+		. = 15 ;
+		BYTE(0x00);
+	} 
+	/DISCARD/ : {
+		*(*)
+	}
+}

src/cpu/p6/mtrr.c

@@ -214,8 +214,6 @@ static __inline__ unsigned int fms(unsigned int x)
  * or a 156MB (128MB + 32MB - 4MB SMA) example:
  *	ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
  */
-#ifdef INTEL_PPRO_MTRR
-
 /* 2 MTRRS are reserved for the operating system */
 #define BIOS_MTRRS 6
 #define OS_MTRRS   2
@@ -291,4 +289,3 @@ void setup_mtrrs(unsigned long ramsizeK)
 	intel_enable_fixed_mtrr();
 	intel_enable_var_mtrr();
 }
-#endif /* INTEL_PPRO_MTRR */