Compile fixes from linuxBIOS hopefully it works for everyone again.
crt0.base
- SMP compile fixes
- No longer unconditionally include cpu/p5/start32.inc
(it's been renamed cpu/i386/entry16.inc)
ldscript.base
- Simplfied, and moved some content into reset16.lds and entry16.lds
stddef.h
- Use C style comments for #endif /* I386_STDDEF_H */
pirq_routing.h
- The define is HAVE_PIRQ_TABLE not HAVE_PIRQ_ROUTING_TABLE
mtrr.c
- Remove the need for defining INTEL_PPRO_MTRR
mainboard/xxx/Config
- start32.inc is no longer automatically included include
entry16.inc and reset16.inc where appropriate
In particular if we are using a docipl we don't want
reset16.inc or reset16.lds
tyan/guiness/mptable.c
- Removed spurious define USE_ALL_CPUS
northbridge/intel/440gx/
- Updated to compile with the factored generic memory code.
nortsouthbridge/sis/xxx/
- Remove includes of northsouthbridge/sis/630/param.h did I add them?
The file is gone now so including it is just bad...
NLBConfig.py
- Allow relative filename arguments
- Add directive ldscript to add an include file into
our linker script
- Fixed docipl to use strings when calling set_option
- Allow target the target directive to use relative paths
- Add extra dependencies to ldscript.lds
This commit is contained in:
Eric W. Biederman
parent
4653e0366a
commit
e1b09246c2
37 changed files with 312 additions and 73 deletions
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@ -7,6 +7,9 @@
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#include <arch/intel.h>
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#include <pciconf.h>
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#ifdef SMP
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#include <cpu/p6/apic.h>
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#endif
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/*
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* This is the entry code (the mkrom(8) utility makes a jumpvector
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* to this adddess.
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@ -20,9 +23,6 @@
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* %fl = 0x0002
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*/
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.text
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.code16
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#include <cpu/p5/start32.inc>
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CRT0_PARAMETERS
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@ -121,17 +121,3 @@ str_after_ram: .string "Ram Initialize?\r\n"
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str_after_copy: .string "after copy?\r\n"
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str_pre_main: .string "before main\r\n"
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newline: .string "\r\n"
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.section ".reset_vector"
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.code16
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.globl EXT(reset_vector)
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EXT(reset_vector):
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#if _ROMBASE >= 0xffff0000
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jmp EXT(_start)
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#elif (_ROMBASE < 0x100000)
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ljmp $((_ROMBASE & 0xf0000)>>4),$EXT(_start_offset);
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#else
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#error _ROMBASE is an unsupported value
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#endif
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@ -9,9 +9,6 @@
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* _ROMBASE
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* : linuxbios text
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* : readonly text
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*
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* _ROMTOP : The top of the rom used where we
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* need to put the reset vector.
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*/
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/*
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* Bootstrap code for the STPC Consumer
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@ -21,9 +18,6 @@
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*
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*/
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_ROMTOP = (_ROMBASE >= 0xffff0000)? 0xfffffff0 : 0xffff0;
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_start_offset = _start & 0xffff;
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gdtptr_offset = gdtptr & 0xffff;
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/*
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* Written by Johan Rydberg, based on work by Daniel Kahlin.
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* Rewritten by Eric Biederman
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@ -35,11 +29,6 @@ gdtptr_offset = gdtptr & 0xffff;
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OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
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OUTPUT_ARCH(i386)
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/*
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* Entry point is not really nececary, since the mkrom(8)
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* tool creates a entry point that jumps to $0xc000:0x0000.
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*/
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/* baloney, but ... RGM*/
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ENTRY(_start)
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SECTIONS
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@ -52,7 +41,6 @@ SECTIONS
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.text (.) : {
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_text = .;
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*(.text);
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*(.text.*)
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_etext = .;
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}
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.rodata (.) : {
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@ -73,8 +61,6 @@ SECTIONS
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.data (.): AT(_erodata) {
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_data = .;
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*(.data)
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*(.sdata)
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*(.sdata2)
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_edata = .;
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}
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_ldata = LOADADDR(.data);
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@ -105,14 +91,8 @@ SECTIONS
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. = ((MAX_CPUS) * (STACK_SIZE));
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_estack = .;
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}
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_lreset = _ROMTOP;
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. = _lreset;
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.reset (.) : AT (_lreset) {
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*(.reset_vector)
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. = 15 ;
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BYTE(0x00);
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}
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_elreset = _lreset + SIZEOF(.reset);
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/DISCARD/ : {
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*(*)
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}
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@ -12,4 +12,4 @@ typedef unsigned int wint_t;
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#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
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#endif //I386_STDDEF_H
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#endif /* I386_STDDEF_H */
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137
src/cpu/i386/entry16.inc
Normal file
137
src/cpu/i386/entry16.inc
Normal file
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@ -0,0 +1,137 @@
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/*
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This software and ancillary information (herein called SOFTWARE )
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called LinuxBIOS is made available under the terms described
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here. The SOFTWARE has been approved for release with associated
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LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
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been authored by an employee or employees of the University of
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California, operator of the Los Alamos National Laboratory under
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Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
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U.S. Government has rights to use, reproduce, and distribute this
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SOFTWARE. The public may copy, distribute, prepare derivative works
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and publicly display this SOFTWARE without charge, provided that this
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Notice and any statement of authorship are reproduced on all copies.
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Neither the Government nor the University makes any warranty, express
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or implied, or assumes any liability or responsibility for the use of
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this SOFTWARE. If SOFTWARE is modified to produce derivative works,
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such modified SOFTWARE should be clearly marked, so as not to confuse
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it with the version available from LANL.
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*/
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/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
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* rminnich@lanl.gov
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*/
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/** Start code to put an i386 or later processor into 32-bit
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* protected mode.
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*/
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.text
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.code16
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.globl EXT(_start)
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.type EXT(_start), @function
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/// We have a relative jump here to around the GDT.
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EXT(_start): jmp _realstart
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/** This gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
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* at 0x18; these are Linux-compatible.
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*/
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/** GDT. we have modified this from the original freebios to make it
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* compatible with linux. This puts text at seg 0x10 and data at 0x18
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*/
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.globl EXT(gdtptr)
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EXT(gdtptr):
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.word 4*8-1
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.long gdt /* we know the offset */
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gdt:
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.word 0x0000, 0x0000 /* dummy */
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.byte 0x0, 0x0, 0x0, 0x0
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.word 0x0000, 0x0000 /* dummy */
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.byte 0x0, 0x0, 0x0, 0x0
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.word 0xffff, 0x0000 /* flat code segment */
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.byte 0x0, 0x9a, 0xcf, 0x0
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.word 0xffff, 0x0000 /* flat data segment */
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.byte 0x0, 0x92, 0xcf, 0x0
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_realstart:
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cli
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/* thanks to kmliu@sis.tw.com for this TBL fix ... */
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/**/
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/* IMMEDIATELY invalidate the translation lookaside buffer before executing*/
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/* any further code. Even though paging is we, disabled could still get*/
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/*false address translations due to the TLB if we didn't invalidate it.*/
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/**/
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xor %eax, %eax
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mov %eax, %cr3 /* Invalidate TLB*/
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/* invalidate the cache */
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invd
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/* Note: gas handles memory addresses in 16 bit code very poorly.
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* In particular it doesn't appear to have a directive allowing you
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* associate a section or even an absolute offset with a segment register.
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*
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* This means that anything except cs:ip relative offsets are
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* a real pain in 16 bit mode. And explains why it is almost
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* imposible to get gas to do lgdt correctly.
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*
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* One way to work around this is to have the linker do the
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* math instead of the assembler. This solves the very
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* pratical problem of being able to write code that can
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* be relocated.
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*
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* An lgdt call before we have memory enabled cannot be
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* position independent, as we cannot execute a call
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* instruction to get our current instruction pointer.
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* So while this code is relocateable it isn't arbitrarily
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* relocatable.
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*
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* In particular this code can be run with the base address of
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* the code segment at either 0xffff0000 or 0xf0000.
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* The first is what is initiallly loaded when the processor
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* powers on. The second is normal real mode segment 0xf000.
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*
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* At this point all the linker script does when calculating
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* gdtptr_offset is return the low 16 bits so your segment
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* must be 64K aligned. So it wouldn't be too much work
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* to support other segments, I just don't see the point
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* right now.
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*/
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data32 lgdt %cs:EXT(gdtptr_offset)
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movl %cr0, %eax
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andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
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orl $0x60000001, %eax /* CD, NW, PE = 1 */
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movl %eax, %cr0
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/* Now that we are in protected mode jump to a 32 bit code segment. */
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data32 ljmp $0x10, $.Lprotected
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/*
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* When we come here we are in protected mode. We expand
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* the stack and copies the data segment from ROM to the
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* memory.
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*
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* After that, we call the chipset bootstrap routine that
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* does what is left of the chipset initialization.
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*
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* NOTE aligned to 4 so that we are sure that the prefetch
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* cache will be reloaded.
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*/
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.align 4
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.Lprotected:
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.code32
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intel_chip_post_macro(0x10) /* post 10 */
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movw $0x18, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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2
src/cpu/i386/entry16.lds
Normal file
2
src/cpu/i386/entry16.lds
Normal file
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@ -0,0 +1,2 @@
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gdtptr_offset = gdtptr & 0xffff;
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_start_offset = _start & 0xffff;
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5
src/cpu/i386/entry32.inc
Normal file
5
src/cpu/i386/entry32.inc
Normal file
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@ -0,0 +1,5 @@
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/* For starting linuxBIOS in protected mode */
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.text
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.align 4
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.code32
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intel_chip_post_macro(0x10) /* post 10 */
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24
src/cpu/i386/reset16.inc
Normal file
24
src/cpu/i386/reset16.inc
Normal file
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@ -0,0 +1,24 @@
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.section ".text.reset_vector"
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.code16
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.globl EXT(reset_vector)
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EXT(reset_vector):
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#if _ROMBASE >= 0xffff0000
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/* Hmm.
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* _start_offset is the low 16 bits of _start.
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* Theoretically we should have problems but it compiles
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* and links properly with binutils 2.9.5 & 2.10.90
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* This is probably a case that needs fixing in binutils.
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* And then we can just use _start.
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* We also need something like the assume directive in
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* other assemblers to tell it where the segment registers
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* are pointing in memory right now.
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*/
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jmp EXT(_start_offset)
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#elif (_ROMBASE < 0x100000)
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ljmp $((_ROMBASE & 0xf0000)>>4),$EXT(_start_offset);
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#else
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#error _ROMBASE is an unsupported value
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#endif
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.text
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.code32
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17
src/cpu/i386/reset16.lds
Normal file
17
src/cpu/i386/reset16.lds
Normal file
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@ -0,0 +1,17 @@
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/*
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* _ROMTOP : The top of the rom used where we
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* need to put the reset vector.
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*/
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_ROMTOP = (_ROMBASE >= 0xffff0000)? 0xfffffff0 : 0xffff0;
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SECTIONS {
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. = _ROMTOP;
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.text.reset_vector (.): {
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*(.text.reset_vector)
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. = 15 ;
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BYTE(0x00);
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}
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/DISCARD/ : {
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*(*)
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}
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}
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@ -214,8 +214,6 @@ static __inline__ unsigned int fms(unsigned int x)
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* or a 156MB (128MB + 32MB - 4MB SMA) example:
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* ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
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*/
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#ifdef INTEL_PPRO_MTRR
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/* 2 MTRRS are reserved for the operating system */
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#define BIOS_MTRRS 6
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#define OS_MTRRS 2
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@ -291,4 +289,3 @@ void setup_mtrrs(unsigned long ramsizeK)
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intel_enable_fixed_mtrr();
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intel_enable_var_mtrr();
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}
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#endif /* INTEL_PPRO_MTRR */
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@ -1,4 +1,6 @@
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arch i386
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mainboardinit cpu/i386/entry32.inc
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mainboardinit superio/acer/m1535/setup_serial.inc
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mainboardinit pc80/serial.inc
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northbridge acer/m1631
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@ -1,4 +1,9 @@
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arch i386
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mainboardinit cpu/i386/entry16.inc
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ldscript cpu/i386/entry16.lds
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mainboardinit cpu/i386/reset16.inc
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ldscript cpu/i386/reset16.lds
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mainboardinit superio/SMC/fdc37b907/setup_serial.inc
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mainboardinit pc80/serial.inc
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northbridge intel/440bx
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@ -1,4 +1,9 @@
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arch i386
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mainboardinit cpu/i386/entry16.inc
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ldscript cpu/i386/entry16.lds
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mainboardinit cpu/i386/reset16.inc
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ldscript cpu/i386/reset16.lds
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mainboardinit superio/ITE/it8671f/setup_serial.inc
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mainboardinit pc80/serial.inc
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northbridge intel/440bx
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@ -1,4 +1,9 @@
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arch i386
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mainboardinit cpu/i386/entry16.inc
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ldscript cpu/i386/entry16.lds
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mainboardinit cpu/i386/reset16.inc
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ldscript cpu/i386/reset16.lds
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mainboardinit superio/SMC/fdc37c669/setup_serial.inc
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mainboardinit pc80/serial.inc
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northbridge intel/440bx
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@ -1,4 +1,9 @@
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arch i386
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mainboardinit cpu/i386/entry16.inc
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ldscript cpu/i386/entry16.lds
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mainboardinit cpu/i386/reset16.inc
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ldscript cpu/i386/reset16.lds
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mainboardinit superio/NSC/pc87309/setup_serial.inc
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mainboardinit pc80/serial.inc
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northbridge intel/440gx
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@ -16,6 +21,7 @@ option L440GX
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option IOAPIC=1
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option SMP=1
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option MAX_CPUS=2
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option HAVE_MP_TABLE=1
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object mainboard.o
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object mptable.o
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@ -1,5 +1,6 @@
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#include <cpu/p6/mpspec.h>
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#include <arch/smp/mpspec.h>
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#include <string.h>
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#include <printk.h>
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void smp_write_config_table(void *v)
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{
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|
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@ -1,4 +1,9 @@
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arch i386
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mainboardinit cpu/i386/entry16.inc
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ldscript cpu/i386/entry16.lds
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mainboardinit cpu/i386/reset16.inc
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ldscript cpu/i386/reset16.lds
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mainboardinit superio/SMC/fdc37n769/setup_serial.inc
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mainboardinit pc80/serial.inc
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northbridge intel/440bx
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|
|
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|
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@ -1,4 +1,9 @@
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arch i386
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mainboardinit cpu/i386/entry16.inc
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ldscript cpu/i386/entry16.lds
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mainboardinit cpu/i386/reset16.inc
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ldscript cpu/i386/reset16.lds
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mainboardinit superio/winbond/w83977ef/setup_serial.inc
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mainboardinit pc80/serial.inc
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northbridge intel/440bx
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|
|
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|
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@ -1,4 +1,7 @@
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arch i386
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mainboardinit cpu/i386/entry16.inc
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ldscript cpu/i386/entry16.lds
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mainboardinit superio/sis/950/setup_serial.inc
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mainboardinit pc80/serial.inc
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northsouthbridge sis/630
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|
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@ -8,7 +11,7 @@ mainboardinit cpu/p6/earlymtrr.inc
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option ENABLE_FIXED_AND_VARIABLE_MTRRS
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option FINAL_MAINBOARD_FIXUP
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option HAVE_PIRQ_TABLE
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option HAVE_PIRQ_TABLE=1
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object mainboard.o
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object irq_tables.o
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keyboard pc80
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|
|
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|
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@ -1,4 +1,7 @@
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arch i386
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mainboardinit cpu/i386/entry16.inc
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ldscript cpu/i386/entry16.lds
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mainboardinit superio/sis/950/setup_serial.inc
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mainboardinit pc80/serial.inc
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||||
northsouthbridge sis/630
|
||||
|
|
|
|||
|
|
@ -1,4 +1,9 @@
|
|||
arch i386
|
||||
mainboardinit cpu/i386/entry16.inc
|
||||
ldscript cpu/i386/entry16.lds
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript cpu/i386/reset16.lds
|
||||
|
||||
mainboardinit superio/acer/m1535/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northbridge acer/m1631
|
||||
|
|
|
|||
|
|
@ -1,4 +1,7 @@
|
|||
arch i386
|
||||
mainboardinit cpu/i386/entry16.inc
|
||||
ldscript cpu/i386/entry16.lds
|
||||
|
||||
mainboardinit superio/sis/950/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northsouthbridge sis/730
|
||||
|
|
|
|||
|
|
@ -1,4 +1,7 @@
|
|||
arch i386
|
||||
mainboardinit cpu/i386/entry16.inc
|
||||
ldscript cpu/i386/entry16.lds
|
||||
|
||||
mainboardinit superio/sis/950/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northsouthbridge sis/540
|
||||
|
|
|
|||
|
|
@ -1,4 +1,7 @@
|
|||
arch i386
|
||||
mainboardinit cpu/i386/entry16.inc
|
||||
ldscript cpu/i386/entry16.lds
|
||||
|
||||
northsouthbridge sis/550
|
||||
mainboardinit cpu/p6/earlymtrr.inc
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,9 @@
|
|||
arch i386
|
||||
mainboardinit cpu/i386/entry16.inc
|
||||
ldscript cpu/i386/entry16.lds
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript cpu/i386/reset16.lds
|
||||
|
||||
mainboardinit northbridge/amd/amd76x/reset_test.inc
|
||||
mainboardinit cpu/k7/earlymtrr.inc
|
||||
mainboardinit northbridge/amd/amd76x/mpinit.inc
|
||||
|
|
|
|||
|
|
@ -3,7 +3,6 @@
|
|||
#include <printk.h>
|
||||
#include <cpu/p6/apic.h>
|
||||
|
||||
#define USE_ALL_CPUS 1
|
||||
void smp_write_config_table(void *v)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
|
|
|
|||
|
|
@ -1,4 +1,9 @@
|
|||
arch i386
|
||||
mainboardinit cpu/i386/entry16.inc
|
||||
ldscript cpu/i386/entry16.lds
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript cpu/i386/reset16.lds
|
||||
|
||||
mainboardinit superio/winbond/w83977ef/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
mainboardinit northbridge/via/vt8601/raminit.inc
|
||||
|
|
|
|||
|
|
@ -1,4 +1,9 @@
|
|||
arch i386
|
||||
mainboardinit cpu/i386/entry16.inc
|
||||
ldscript cpu/i386/entry16.lds
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript cpu/i386/reset16.lds
|
||||
|
||||
mainboardinit superio/via/vt82c686/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northbridge via/vt8601
|
||||
|
|
|
|||
|
|
@ -1,4 +1,7 @@
|
|||
arch i386
|
||||
mainboardinit cpu/i386/entry16.inc
|
||||
ldscript cpu/i386/entry16.lds
|
||||
|
||||
mainboardinit superio/via/vt82c686/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northbridge via/vt8601
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
raminit northbridge/intel/440gx/raminit.inc
|
||||
raminit sdram/generic_sdram.inc
|
||||
raminit sdram/generic_sdram_enable.inc
|
||||
mainboardinit northbridge/intel/440gx/raminit.inc
|
||||
mainboardinit sdram/generic_sdram_enable.inc
|
||||
mainboardinit sdram/generic_sdram.inc
|
||||
mainboardinit sdram/generic_zero_ecc_sdram.inc
|
||||
|
||||
object northbridge.o
|
||||
|
|
|
|||
|
|
@ -968,17 +968,14 @@ ram_set_spd_registers:
|
|||
#endif
|
||||
RET_LABEL(ram_set_spd_registers)
|
||||
|
||||
#if 1
|
||||
#define HAVE_ECC_RAM_SIZE
|
||||
get_ecc_ram_size_ebx:
|
||||
get_ecc_ram_size_bytes_ebx:
|
||||
/* FIXME handle the no ram case. */
|
||||
movl $0x67, %eax /* Read the RAM SIZE */
|
||||
PCI_READ_CONFIG_BYTE
|
||||
andl $0x000000ff, %eax /* Convert it to bytes */
|
||||
movl %eax, %ebx
|
||||
shll $23, %ebx
|
||||
RET_LABEL(get_ecc_ram_size_ebx)
|
||||
#endif /* HAVE_ECC_RAM_SIZE */
|
||||
|
||||
RET_LABEL(get_ecc_ram_size_bytes_ebx)
|
||||
|
||||
/* things that are not used */
|
||||
#define FIRST_NORMAL_REFERENCE()
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ static char rcsid[] =
|
|||
#include <subr.h>
|
||||
#include <pci.h>
|
||||
#include <pci_ids.h>
|
||||
#include <northsouthbridge/sis/630/param.h>
|
||||
|
||||
/* these functions query the hardware to figure out how much ram is in
|
||||
* the machine. They then place that information in the parameter block.
|
||||
|
|
|
|||
|
|
@ -16,8 +16,7 @@ static char rcsid[] =
|
|||
#include <subr.h>
|
||||
#include <pci.h>
|
||||
#include <pci_ids.h>
|
||||
#include <northsouthbridge/sis/630/param.h>
|
||||
#include <cpu/p5/io.h>
|
||||
#include <arch/io.h>
|
||||
|
||||
void keyboard_on()
|
||||
{
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ static char rcsid[] =
|
|||
#include <subr.h>
|
||||
#include <pci.h>
|
||||
#include <pci_ids.h>
|
||||
#include <northsouthbridge/sis/630/param.h>
|
||||
|
||||
/* these functions query the hardware to figure out how much ram is in
|
||||
* the machine. They then place that information in the parameter block.
|
||||
|
|
|
|||
|
|
@ -16,8 +16,7 @@ static char rcsid[] =
|
|||
#include <subr.h>
|
||||
#include <pci.h>
|
||||
#include <pci_ids.h>
|
||||
#include <northsouthbridge/sis/630/param.h>
|
||||
#include <cpu/p5/io.h>
|
||||
#include <arch/io.h>
|
||||
|
||||
void keyboard_on()
|
||||
{
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ static char rcsid[] =
|
|||
#include <subr.h>
|
||||
#include <pci.h>
|
||||
#include <pci_ids.h>
|
||||
#include <northsouthbridge/sis/630/param.h>
|
||||
|
||||
/* these functions query the hardware to figure out how much ram is in
|
||||
* the machine. They then place that information in the parameter block.
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ static char rcsid[] =
|
|||
#include <subr.h>
|
||||
#include <pci.h>
|
||||
#include <pci_ids.h>
|
||||
#include <northsouthbridge/sis/630/param.h>
|
||||
#include <cpu/p5/io.h>
|
||||
|
||||
void keyboard_on()
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue