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UPSTREAM: amd/pi/hudson: Add TPM decode to SPI function

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Add a function to send the TPM decode to the SPI interface.
Enables use of SPI TPMs on Hudson mainboards.

BUG=none
BRANCH=none
TEST=none

Change-Id: I7ae140e18c3e0a3c43e72dcb899ee8bd68beb945
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6fcaaef614
Original-Change-Id: I0e85ed92163e38eca6a55456708ab322d6a90d4c
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19402
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/488060
This commit is contained in:
Marc Jones 2017-04-20 16:48:42 -06:00 • committed by chrome-bot
commit e18948a266
3 changed files with 16 additions and 4 deletions
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9
src/southbridge/amd/pi/hudson/early_setup.c
View file

@ -327,4 +327,13 @@ void hudson_read_mode(u32 mode)
& ~SPI_READ_MODE_MASK) | mode);
}
void hudson_tpm_decode_spi(void)
{
device_t dev = PCI_DEV(0, 0x14, 3); /* LPC device */
u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase
| ROUTE_TPM_2_SPI);
}
#endif

4
src/southbridge/amd/pi/hudson/hudson.h
View file

@ -69,6 +69,7 @@
#define REV_HUDSON_A12 0x12
#define SPIROM_BASE_ADDRESS_REGISTER 0xA0
#define ROUTE_TPM_2_SPI BIT(3)
#define SPI_ROM_ENABLE 0x02
#define SPI_BASE_ADDRESS 0xFEC10000
@ -188,8 +189,7 @@ void hudson_disable_4dw_burst(void);
void hudson_set_readspeed(u16 norm, u16 fast);
void lpc_wideio_512_window(uint16_t base);
void lpc_wideio_16_window(uint16_t base);
void hudson_tpm_decode_spi(void);
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
#if IS_ENABLED(CONFIG_HUDSON_UART)

7
src/southbridge/amd/pi/hudson/lpc.c
View file

@ -126,10 +126,13 @@ static void hudson_lpc_read_resources(device_t dev)
static void hudson_lpc_set_resources(struct device *dev)
{
struct resource *res;
u32 spi_enable_bits;
/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
/* Special case. The SpiRomEnable and other enables should STAY set. */
res = find_resource(dev, 2);
pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
spi_enable_bits &= 0xF;
pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | spi_enable_bits);
pci_dev_set_resources(dev);
}