diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 29b404ac3d..59c7b3a277 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -456,6 +456,51 @@ config CMOS_RECOVERY_BYTE
 	  This is the byte before the default first byte used by VBNV
 	  (0x26 + 0x0E - 1)
 
+menu "RAS Config Options"
+choice
+	prompt "PCIe AER Report Mechanism"
+	depends on SOC_AMD_FAEGAN
+	default AMD_PCIE_AER_OS_FIRST_HANDLING
+	help
+	  Choose a PCIe AER Report Mechanism.
+
+config AMD_PCIE_AER_PFEH_FIRMWARE_FIRST_REPORTING
+	bool "PFEH-based Firmware First reporting"
+
+config AMD_PCIE_AER_OS_FIRST_HANDLING
+	bool "OS First handling"
+
+config AMD_PCIE_AER_FIRMWARE_FIRST_HANDLING
+	bool "Firmware First handling through SMI"
+endchoice
+
+choice
+	prompt "AMD NBIO Ras Control V2"
+	depends on SOC_AMD_FAEGAN
+	default AMD_NBIO_RAS_MCA_REPORTING if SOC_AMD_FAEGAN
+	default AMD_NBIO_RAS_DISABLE
+	help
+	  Choose an AMD NBIO RAS control option.
+
+config AMD_NBIO_RAS_DISABLE
+	bool "Disable NBIO Ras Control"
+
+config AMD_NBIO_RAS_MCA_REPORTING
+	bool "MCA reporting"
+
+config AMD_NBIO_RAS_LEGACY_MODE
+	bool "Legacy Mode"
+endchoice
+
+config AMD_PCIE_ECRC_ENABLEMENT
+	bool "PCIe ECRC Enablement"
+	depends on SOC_AMD_FAEGAN
+	default y if SOC_AMD_FAEGAN
+	default n
+	help
+	  Enable/Disable PCIe ECRC support.
+endmenu
+
 if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
 
 config RWA_REGION_ONLY
diff --git a/src/soc/amd/glinda/fsp_m_params.c b/src/soc/amd/glinda/fsp_m_params.c
index ff5f04c7f2..cff9b01ae2 100644
--- a/src/soc/amd/glinda/fsp_m_params.c
+++ b/src/soc/amd/glinda/fsp_m_params.c
@@ -160,6 +160,31 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	mcfg->enable_nb_azalia = is_dev_enabled(DEV_PTR(gfx_hda));
 	mcfg->hda_enable = is_dev_enabled(DEV_PTR(hda));
 
+	/* Faegan only: RAS Config Options */
+	if (CONFIG(SOC_AMD_FAEGAN)) {
+		if (CONFIG(AMD_PCIE_AER_OS_FIRST_HANDLING))
+			mcfg->amd_pcie_aer_report_mechanism = 1;
+		else if (CONFIG(AMD_PCIE_AER_FIRMWARE_FIRST_HANDLING))
+			mcfg->amd_pcie_aer_report_mechanism = 2;
+		else
+			mcfg->amd_pcie_aer_report_mechanism = 0;
+
+		if (CONFIG(AMD_NBIO_RAS_MCA_REPORTING))
+			mcfg->amd_nbio_ras_controlv2 = 1;
+		else if (CONFIG(AMD_NBIO_RAS_LEGACY_MODE))
+			mcfg->amd_nbio_ras_controlv2 = 2;
+		else
+			mcfg->amd_nbio_ras_controlv2 = 0;
+
+		mcfg->pcie_ecrc_enablement = CONFIG(AMD_PCIE_ECRC_ENABLEMENT);
+		printk(BIOS_SPEW, "mcfg->amd_pcie_aer_report_mechanism %x\n",
+		       mcfg->amd_pcie_aer_report_mechanism);
+		printk(BIOS_SPEW, "mcfg->amd_nbio_ras_controlv2 %x\n",
+		       mcfg->amd_nbio_ras_controlv2);
+		printk(BIOS_SPEW, "mcfg->pcie_ecrc_enablement %x\n",
+		       mcfg->pcie_ecrc_enablement);
+	}
+
 	if (config->usb_phy_custom) {
 		/* devicetree config is const, use local copy */
 		static struct usb_phy_config lcl_usb_phy;