From e0209799932395a246d6b31d892cf49d51e85617 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Wed, 14 May 2025 10:37:11 +0200 Subject: [PATCH] mb/siemens/mc_rpl: Adjust the flash map file Rename chromeos.fmd to mc_rpl.fmd and adjust the flash layout settings to match the needs of this board. There is e.g. no A/B scheme used and CSME stitching is done externally, therefore no detailed CSME partitions are required at all. Change-Id: I6389960d816c5f1a4690a965961301d3797305ff Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/87665 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/mainboard/siemens/mc_rpl/Kconfig | 5 ++- src/mainboard/siemens/mc_rpl/chromeos.fmd | 54 ----------------------- src/mainboard/siemens/mc_rpl/mc_rpl.fmd | 14 ++++++ 3 files changed, 18 insertions(+), 55 deletions(-) delete mode 100644 src/mainboard/siemens/mc_rpl/chromeos.fmd create mode 100644 src/mainboard/siemens/mc_rpl/mc_rpl.fmd diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig index 698df3c4d0..b1f7262681 100644 --- a/src/mainboard/siemens/mc_rpl/Kconfig +++ b/src/mainboard/siemens/mc_rpl/Kconfig @@ -2,7 +2,7 @@ config BOARD_SIEMENS_BASEBOARD_MC_RPL def_bool n - select BOARD_ROMSIZE_KB_32768 + select BOARD_ROMSIZE_KB_16384 select CPU_INTEL_SOCKET_LGA1700 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID @@ -79,6 +79,9 @@ config DEVICETREE config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_rpl.fmd" + choice prompt "ON BOARD EC" default MC_RPL_CHROME_EC if BOARD_SIEMENS_MC_RPL1 diff --git a/src/mainboard/siemens/mc_rpl/chromeos.fmd b/src/mainboard/siemens/mc_rpl/chromeos.fmd deleted file mode 100644 index 0e8d321f85..0000000000 --- a/src/mainboard/siemens/mc_rpl/chromeos.fmd +++ /dev/null @@ -1,54 +0,0 @@ -FLASH 32M { - SI_ALL 6M { - SI_DESC 4K - SI_EC 512K - SI_ME { - CSE_LAYOUT 8K - CSE_RO 1588K - CSE_DATA 512K - # 64-KiB aligned to optimize RW erases during CSE update. - CSE_RW 3520K - } - } - SI_BIOS 26M { - RW_SECTION_A 8M { - VBLOCK_A 64K - FW_MAIN_A(CBFS) - RW_FWID_A 64 - } - RW_LEGACY(CBFS) 1M - RW_MISC 1M { - UNIFIED_MRC_CACHE(PRESERVE) 192K { - RECOVERY_MRC_CACHE 64K - RW_MRC_CACHE 128K - } - RW_ELOG(PRESERVE) 16K - RW_SHARED 16K { - SHARED_DATA 8K - VBLOCK_DEV 8K - } - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 24K - } - # This section starts at the 16M boundary in SPI flash. - # ADL does not support a region crossing this boundary, - # because the SPI flash is memory-mapped into two non- - # contiguous windows. - RW_SECTION_B 8M { - VBLOCK_B 64K - FW_MAIN_B(CBFS) - RW_FWID_B 64 - } - # Make WP_RO region align with SPI vendor - # memory protected range specification. - WP_RO 8M { - RO_VPD(PRESERVE) 16K - RO_SECTION { - FMAP 2K - RO_FRID 64 - GBB@4K 448K - COREBOOT(CBFS) - } - } - } -} diff --git a/src/mainboard/siemens/mc_rpl/mc_rpl.fmd b/src/mainboard/siemens/mc_rpl/mc_rpl.fmd new file mode 100644 index 0000000000..ddb30df8aa --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/mc_rpl.fmd @@ -0,0 +1,14 @@ +FLASH CONFIG_ROM_SIZE { + SI_ALL 5M { + SI_DESC 4K + SI_ME 5116K + } + SI_BIOS 11M { + FMAP 2K + UNIFIED_MRC_CACHE(PRESERVE) 192K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 128K + } + COREBOOT(CBFS) + } +}