From dfd82d2608be110e677eedd0270e58ec25e0a0bf Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Mon, 19 Aug 2024 03:23:08 +0000
Subject: [PATCH] mb/lenovo/thinkcentre_m710s: Drop PCH UPDs from PEG device

Change-Id: Ic0e0864b99c5078e5b84b9183262b3c47ffcb329
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
index bce93ae7e4..4d1828c5ab 100644
--- a/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
+++ b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
@@ -9,13 +9,6 @@ chip soc/intel/skylake
 			                 "SlotLengthLong"
 			                 "PCIE16X"
 			                 "SlotDataBusWidth16X"
-
-			# These configurations are technically for PCIe root
-			# ports. However, they are used as there is no
-			# equivalent for PEG devices.
-			register "PcieRpClkReqSupport[0]" = "true"
-			register "PcieRpClkReqNumber[0]"  = "2"
-			register "PcieRpClkSrcNumber[0]"  = "0"
 		end
 		device ref igpu		on  end
 		device ref south_xhci	on