diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index c0005bf802..891b3abffd 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -228,7 +228,7 @@ static const io_register_t pch_gpio_registers[] = { { 0x40, 4, "GPIO_USE_SEL3" }, { 0x44, 4, "GP_IO_SEL3" }, { 0x48, 4, "GP_LVL3" }, - { 0x4c, 4, "RESERVED" }, + { 0x4c, 4, "GPI_INV2" }, // GPIO Signal Invert 2 { 0x50, 4, "RESERVED" }, { 0x54, 4, "RESERVED" }, { 0x58, 4, "RESERVED" }, @@ -861,6 +861,9 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) case PCI_DEVICE_ID_INTEL_HM97: case PCI_DEVICE_ID_INTEL_Z97: case PCI_DEVICE_ID_INTEL_H97: + case PCI_DEVICE_ID_INTEL_WELLSBURG_SUPER: + case PCI_DEVICE_ID_INTEL_WELLSBURG_C612: + case PCI_DEVICE_ID_INTEL_WELLSBURG_X99: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = pch_gpio_registers; size = ARRAY_SIZE(pch_gpio_registers); diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 66d42a903d..05d5c092fd 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -447,6 +447,9 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z97, "Z97"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H97, "H97"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SUPER, "Wellsburg Super SKU" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_C612, "Wellsburg C612" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_X99, "Wellsburg X99" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK_LPC, "Gemini Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H510, "H510" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 3a173da19c..e38fb190bb 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -309,6 +309,9 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_HM97 0x8cc3 #define PCI_DEVICE_ID_INTEL_Z97 0x8cc4 #define PCI_DEVICE_ID_INTEL_H97 0x8cc6 +#define PCI_DEVICE_ID_INTEL_WELLSBURG_SUPER 0x8d40 +#define PCI_DEVICE_ID_INTEL_WELLSBURG_C612 0x8d44 +#define PCI_DEVICE_ID_INTEL_WELLSBURG_X99 0x8d47 #define PCI_DEVICE_ID_INTEL_82X58 0x3405 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 diff --git a/util/inteltool/lpc.c b/util/inteltool/lpc.c index 0d21bedc80..af452a24d1 100644 --- a/util/inteltool/lpc.c +++ b/util/inteltool/lpc.c @@ -9,6 +9,47 @@ #define SUNRISE_LPC_BC 0xdc +static const io_register_t c610_lpc_cfg_registers[] = { + {0x00, 2, "VID"}, // Vendor Identification + {0x02, 2, "DID"}, // Device Identification + {0x04, 2, "PCICMD"}, // PCI Command + {0x06, 2, "PCISTS"}, // PCI Status + {0x08, 1, "RID"}, // Revision Identification + {0x09, 1, "PI"}, // Programming Interface + {0x0A, 1, "SCC"}, // Sub Class Code + {0x0B, 1, "BCC"}, // Base Class Code + {0x0D, 1, "PLT"}, // Primary Latency Timer + {0x0E, 1, "HEADTYP"}, // Header Type + {0x2C, 4, "SS"}, // Sub System Identifiers + {0x40, 4, "PMBASE"}, // ACPI Base Address + {0x44, 1, "ACPI_CNTL"}, // ACPI Control + {0x48, 4, "GPIOBASE"}, // ACPI Base Address + {0x4C, 1, "GC"}, // GPIO Control + {0x60, 4, "PIRQ[n]_ROUT"}, // PIRQ[A-D] Routing Control + {0x64, 1, "SIRQ_CNTL"}, // Serial IRQ Control + {0x68, 4, "PIRQ[n]_ROUT"}, // PIRQ[E-H] Routing Control + {0x6C, 2, "LPC_IBDF"}, // IOxAPIC Bus:Device:Function + {0x70, 8, "LPC_HnBDF"}, // HPET Configuration + {0x80, 1, "LPC_I/O_DEC"}, // I/O Decode + {0x82, 2, "LPC_EN"}, // LPC I/F Enables + {0x84, 4, "GEN1_DEC"}, // LPC I/F Generic Decode Range 1 + {0x88, 4, "GEN2_DEC"}, // LPC I/F Generic Decode Range 2 + {0x8C, 4, "GEN3_DEC"}, // LPC I/F Generic Decode Range 3 + {0x90, 4, "GEN4_DEC"}, // LPC I/F Generic Decode Range 4 00000000h R/W + {0x94, 4, "ULKMC"}, // USB Legacy Keyboard / Mouse Control 00000000h RO, R/WC, R/W, RW1L + {0x98, 4, "LGMR LPC"}, // I/F Generic Memory Range 00000000h R/W + {0xD0, 4, "BIOS_SEL1"}, // BIOS Select + {0xD4, 2, "BIOS_SEL2"}, // BIOS Select + {0xD8, 2, "BIOS_DEC_EN1"}, // BIOS Decode Enable + {0xDC, 1, "BIOS_CNTL"}, // BIOS Control + {0xE0, 2, "FDCAP"}, // Feature Detection Capability ID + {0xE2, 1, "FDLEN"}, // Feature Detection Capability Length + {0xE3, 1, "FDVER"}, // Feature Detection Version + {0xE4, 4, "FVECIDX"}, // Feature Vector Index + {0xE8, 4, "FVECD"}, // Feature Vector Data + {0xF0, 4, "RCBA"}, // Root Complex Base Address +}; + static const io_register_t sunrise_lpc_cfg_registers[] = { {0x00, 4, "ID"}, {0x04, 2, "CMD"}, @@ -109,6 +150,17 @@ int print_lpc(struct pci_dev *sb, struct pci_access *pacc) printf("\n========== LPC/eSPI =========\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_WELLSBURG_SUPER: + case PCI_DEVICE_ID_INTEL_WELLSBURG_C612: + case PCI_DEVICE_ID_INTEL_WELLSBURG_X99: + dev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 0); + if (!dev) { + printf("LPC interface not found.\n"); + return 1; + } + cfg_registers = c610_lpc_cfg_registers; + cfg_registers_size = ARRAY_SIZE(c610_lpc_cfg_registers); + break; case PCI_DEVICE_ID_INTEL_H110: case PCI_DEVICE_ID_INTEL_H170: case PCI_DEVICE_ID_INTEL_Z170: @@ -212,6 +264,13 @@ int print_lpc(struct pci_dev *sb, struct pci_access *pacc) pci_read_long(dev, cfg_registers[i].addr), cfg_registers[i].name); break; + case 3: + printf("0x%04x: 0x%04x%02x (%s)\n", + cfg_registers[i].addr, + pci_read_word(dev, cfg_registers[i].addr), + pci_read_byte(dev, cfg_registers[i].addr + 2), + cfg_registers[i].name); + break; case 2: printf("0x%04x: 0x%04x (%s)\n", cfg_registers[i].addr, diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 716b85ce03..31b3325223 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -97,7 +97,8 @@ static const io_register_t pch_pm_registers[] = { { 0x52, 2, "RESERVED" }, { 0x54, 4, "RESERVED" }, { 0x58, 4, "RESERVED" }, - { 0x5c, 4, "RESERVED" }, + { 0x5c, 2, "ALT_GPI_SMI_EN2" }, // Alternate GPI SMI Enable 2 Register + { 0x5e, 2, "ALT_GPI_SMI_STS2" }, // Alternate GPI SMI Status 2 Register /* The TCO registers start here. */ { 0x60, 2, "TCO_RLD" }, { 0x62, 1, "TCO_DAT_IN" }, @@ -771,6 +772,9 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_HM97: case PCI_DEVICE_ID_INTEL_Z97: case PCI_DEVICE_ID_INTEL_H97: + case PCI_DEVICE_ID_INTEL_WELLSBURG_SUPER: + case PCI_DEVICE_ID_INTEL_WELLSBURG_C612: + case PCI_DEVICE_ID_INTEL_WELLSBURG_X99: pmbase = pci_read_word(sb, 0x40) & 0xff80; pm_registers = pch_pm_registers; pm_registers_size = ARRAY_SIZE(pch_pm_registers); diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index 46f7858feb..965c492e8d 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -106,6 +106,9 @@ int print_rcba(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_HM97: case PCI_DEVICE_ID_INTEL_Z97: case PCI_DEVICE_ID_INTEL_H97: + case PCI_DEVICE_ID_INTEL_WELLSBURG_SUPER: + case PCI_DEVICE_ID_INTEL_WELLSBURG_C612: + case PCI_DEVICE_ID_INTEL_WELLSBURG_X99: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index 6e869a2da9..6d6b500eeb 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -321,6 +321,9 @@ static int print_bioscntl(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_HM97: case PCI_DEVICE_ID_INTEL_Z97: case PCI_DEVICE_ID_INTEL_H97: + case PCI_DEVICE_ID_INTEL_WELLSBURG_SUPER: + case PCI_DEVICE_ID_INTEL_WELLSBURG_C612: + case PCI_DEVICE_ID_INTEL_WELLSBURG_X99: case PCI_DEVICE_ID_INTEL_H110: case PCI_DEVICE_ID_INTEL_H170: case PCI_DEVICE_ID_INTEL_Z170: @@ -509,6 +512,9 @@ static int print_spibar(struct pci_dev *sb, struct pci_access *pacc) { case PCI_DEVICE_ID_INTEL_HM97: case PCI_DEVICE_ID_INTEL_Z97: case PCI_DEVICE_ID_INTEL_H97: + case PCI_DEVICE_ID_INTEL_WELLSBURG_SUPER: + case PCI_DEVICE_ID_INTEL_WELLSBURG_C612: + case PCI_DEVICE_ID_INTEL_WELLSBURG_X99: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: