From df4c515d73b02061e5c98f51efd50e04b10d63f5 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Mon, 4 Nov 2013 09:34:04 -0800 Subject: [PATCH] tegra124: add the _x clocks to clock_enable_clear_reset These need to be supported for graphics. BUG=None TEST=Build and boot and it all still works BRANCH=None Change-Id: Ie02cbd3012b320bb59be9e0fb899c09000f29a1b Signed-off-by: Ronald G. Minnich Reviewed-on: https://chromium-review.googlesource.com/175539 Reviewed-by: Julius Werner Commit-Queue: Ronald Minnich Tested-by: Ronald Minnich --- src/mainboard/google/nyan/bootblock.c | 2 +- src/mainboard/google/nyan/mainboard.c | 2 +- src/soc/nvidia/tegra124/clock.c | 4 +++- src/soc/nvidia/tegra124/include/soc/clock.h | 3 ++- 4 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c index ca8eca42da..4ee1aacc88 100644 --- a/src/mainboard/google/nyan/bootblock.c +++ b/src/mainboard/google/nyan/bootblock.c @@ -49,7 +49,7 @@ void bootblock_mainboard_init(void) clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR, CLK_H_I2C5 | CLK_H_APBDMA, - 0, CLK_V_MSELECT, 0); + 0, CLK_V_MSELECT, 0, 0); // I2C5 (PMU) clock. pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX, diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index a25c91cf5d..d768bc608a 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -207,7 +207,7 @@ static void mainboard_init(device_t dev) CLK_H_PMC | CLK_H_MEM | CLK_H_USB3, CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3, CLK_V_I2C4, - CLK_W_DVFS); + CLK_W_DVFS, 0); usb_setup_utmip1(); /* USB2 is the camera, we don't need it in firmware */ diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 02f10a5504..2dd1f17ac6 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -358,13 +358,14 @@ void clock_init(void) writel(val, &clk_rst->clk_sys_rate); } -void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w) +void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) { if (l) writel(l, &clk_rst->clk_enb_l_set); if (h) writel(h, &clk_rst->clk_enb_h_set); if (u) writel(u, &clk_rst->clk_enb_u_set); if (v) writel(v, &clk_rst->clk_enb_v_set); if (w) writel(w, &clk_rst->clk_enb_w_set); + if (x) writel(x, &clk_rst->clk_enb_x_set); /* Give clocks time to stabilize. */ udelay(IO_STABILIZATION_DELAY); @@ -374,4 +375,5 @@ void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w) if (u) writel(u, &clk_rst->rst_dev_u_clr); if (v) writel(v, &clk_rst->rst_dev_v_clr); if (w) writel(w, &clk_rst->rst_dev_w_clr); + if (x) writel(x, &clk_rst->rst_dev_x_clr); } diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index 74f29a1cad..caef0b3d15 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -236,7 +236,8 @@ enum clock_source { /* Careful: Not true for all sources, always check TRM! */ int clock_get_osc_khz(void); void clock_early_uart(void); void clock_cpu0_config_and_reset(void * entry); -void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w); +void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); void clock_init(void); void clock_init_arm_generic_timer(void); #endif /* __SOC_NVIDIA_TEGRA124_CLOCK_H__ */ +