soc/qualcomm/common: Avoid hardcoding SPI bus from QUP range

The `spi_ctrlr_bus_map` defines the range of SPI bus numbers managed
by different controllers. Previously, the generic `spi_qup_ctrlr`
was hardcoded to manage buses 0 through 15.

Modify the `.bus_end` value for the `spi_qup_ctrlr` entry to be
`QUPV3_SE_MAX - 1`.

TEST=Able to build google/herobrine.

Change-Id: I7e9ec555a6d72d93bc23285e48eab52030978e1a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>

src/soc/qualcomm/common/spi.c

@@ -2,6 +2,7 @@
 
 #include <spi-generic.h>
 #include <spi_flash.h>
+#include <soc/qcom_qup_se.h>
 #include <soc/qspi_common.h>
 #include <soc/qupv3_spi_common.h>
 
@@ -29,7 +30,7 @@ const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
 	{
 		.ctrlr = &spi_qup_ctrlr,
 		.bus_start = 0,
-		.bus_end = 15,
+		.bus_end = QUPV3_SE_MAX - 1,
 	},
 };