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arm/exynos: Correct SPI session commands.

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Some initialization / shutdown commands should be paired correctly in a SPI I/O
session. For example, setting CS should be enabled and disabled in each read;
and the bus width (byte or word) should be configured only when opening /
closing the SPI device.

BUG=none
TEST=manually: emerge-daisy chromeos-coreboot-snow; boot on Snow.
BRANCH=none

Change-Id: I1e4532e71fb535453c9fd9151f89dd2aca52e7d0
Reviewed-on: https://gerrit.chromium.org/gerrit/59691
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Hung-Te Lin 2013-06-23 08:14:30 +08:00 • committed by ChromeBot
commit df09a839bc
2 changed files with 14 additions and 12 deletions
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13
src/cpu/samsung/exynos5250/spi.c
View file

@ -102,7 +102,6 @@ int exynos_spi_open(struct exynos_spi *regs)
/* now set rx and tx channel ON */
setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
return 0;
}
@ -110,6 +109,8 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off)
{
int upto, todo;
int i;
clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
/* Send read instruction (0x3h) followed by a 24 bit addr */
writel((SF_READ_DATA_CMD << 24) | off, &regs->tx_data);
@ -123,6 +124,11 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off)
setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
return len;
}
int exynos_spi_close(struct exynos_spi *regs)
{
/*
* Let put controller mode to BYTE as
* SPI driver does not support WORD mode yet
@ -131,11 +137,6 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off)
SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
writel(0, &regs->swap_cfg);
return len;
}
int exynos_spi_close(struct exynos_spi *regs)
{
/*
* Flush spi tx, rx fifos and reset the SPI controller
* and clear rx/tx channel

13
src/cpu/samsung/exynos5420/spi.c
View file

@ -102,7 +102,6 @@ int exynos_spi_open(struct exynos_spi *regs)
/* now set rx and tx channel ON */
setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
return 0;
}
@ -110,6 +109,8 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off)
{
int upto, todo;
int i;
clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
/* Send read instruction (0x3h) followed by a 24 bit addr */
writel((SF_READ_DATA_CMD << 24) | off, &regs->tx_data);
@ -123,6 +124,11 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off)
setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
return len;
}
int exynos_spi_close(struct exynos_spi *regs)
{
/*
* Let put controller mode to BYTE as
* SPI driver does not support WORD mode yet
@ -131,11 +137,6 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off)
SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
writel(0, &regs->swap_cfg);
return len;
}
int exynos_spi_close(struct exynos_spi *regs)
{
/*
* Flush spi tx, rx fifos and reset the SPI controller
* and clear rx/tx channel