erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Support for the Intel ICH7 southbridge.

Browse source 
This includes an early SMI handler.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2008-10-29 04:46:52 +00:00 • committed by Stefan Reinauer
commit debb11fc1f
29 changed files with 3587 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/include/device/device.h
View file

@ -71,7 +71,7 @@ struct device {
struct device_path path;
unsigned vendor;
unsigned device;
unsigned int class; /* 3 bytes: (base,sub,prog-if) */
unsigned int class; /* 3 bytes: (base, sub, prog-if) */
unsigned int hdr_type; /* PCI header type */
unsigned int enabled : 1; /* set if we should enable the device */
unsigned int initialized : 1; /* set if we have initialized the device */
@ -85,7 +85,7 @@ struct device {
struct resource resource[MAX_RESOURCES];
unsigned int resources;
/* link are (down sream) buses attached to the device, usually a leaf
/* link are (down stream) buses attached to the device, usually a leaf
* device with no children have 0 buses attached and a bridge has 1 bus
*/
struct bus link[MAX_LINKS];