From de73f2b080817ec2d8a23919c228ec9141b41c75 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 13 Oct 2016 14:12:45 +0200 Subject: [PATCH] UPSTREAM: nb/i945/gma.c: correct VSYNC end offset According to "G45: Volume 3: Display Register Intel 965G Express Chipset Family and Intel G35 Express Chipset Graphics Controller" the VSYNC end should start at bit 16. This is also how Linux (at least 4.4) sets this register, which can be seen with intel-gpu-tools. TESTED on Lenovo thinkpad X60 (it does not change anything). BUG=None BRANCH=None TEST=None Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/17015 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Reviewed-by: Alexander Couzens Change-Id: Ie222ac13211a91c4fbc580e2bf9de0d973ea9a3a Reviewed-on: https://chromium-review.googlesource.com/400110 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/northbridge/intel/i945/gma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 7fcd67020c..e40b9f00a8 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -275,7 +275,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1)); write32(pmmio + VSYNC(1), - (vactive + bottom_border + vfront_porch + vsync - 1) + ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) | (vactive + bottom_border + vfront_porch - 1)); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)