From de3cdef128966d76e7d8e2ebd641763b911c3ad5 Mon Sep 17 00:00:00 2001 From: William wu Date: Thu, 29 Sep 2016 15:18:41 +0800 Subject: [PATCH] gru: Add USB 2.0 PHY tuning for Kevin PHY0 and PHY1 We found that Kevin board PHY0 and PHY1 eye-diagram margin is not enough to make compliance test pass, and the PHY0 USB SI is worse than PHY1, because of the higher PCB impedance. For PHY0, we can't improve the eye-diagram by SW PHY tuning, so we need to reduce the RBIAS resistance from 133 ohm to 115 ohm, it can help to increase the eye-height. For PHY1, we can improve the eye-diagram by setting the max pre-emphasis level. And after the above change, the USB2 signal amplitude will become larger at the test point near to SOC USB2 PHY, in order to avoid mis-trigger the disconnect detection (650mV), we need to disable pre-emphasize in eop state. BRANCH=None BUG=chrome-os-partner:53863 TEST=do USB 2.0 compliance test for Kevin C0 and C1 port. Change-Id: I00cb325b9938e4276cc77b5d6f5faa7023379608 Signed-off-by: William wu Reviewed-on: https://chromium-review.googlesource.com/390615 Commit-Ready: Julius Werner Tested-by: Julius Werner Reviewed-by: Julius Werner --- src/mainboard/google/gru/mainboard.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index c8f6477268..72deae0b47 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -236,9 +236,17 @@ static void setup_usb(void) /* Set max ODT compensation voltage and current tuning reference. */ write32(&rk3399_grf->usbphy0_ctrl[3], 0x0fff02e3); write32(&rk3399_grf->usbphy1_ctrl[3], 0x0fff02e3); - /* Set max pre-emphasis level, only on Kevin PHY0. */ - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) + /* Set max pre-emphasis level, only on Kevin PHY0 and PHY1, + * and disable the pre-emphasize in eop state to avoid + * mis-trigger the disconnect detection. */ + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) { write32(&rk3399_grf->usbphy0_ctrl[12], 0xffff00a7); + write32(&rk3399_grf->usbphy1_ctrl[12], 0xffff00a7); + write32(&rk3399_grf->usbphy0_ctrl[0], 0x00010000); + write32(&rk3399_grf->usbphy1_ctrl[0], 0x00010000); + write32(&rk3399_grf->usbphy0_ctrl[13], 0x00010000); + write32(&rk3399_grf->usbphy1_ctrl[13], 0x00010000); + } setup_usb_otg0(); setup_usb_otg1();