From dd7956bfc5c8a64a47e82dde06e410c389faf34f Mon Sep 17 00:00:00 2001 From: Sowmya Aralguppe Date: Sun, 15 Jun 2025 23:34:27 +0530 Subject: [PATCH] mb/google/ocelot: Update GPIO table Configure GPIOs and related settings to align with the specifications provided in the schematic_1433518 and platform mapping document version Rev0p85. BUG=b:394208231 TEST=Build Ocelot and verify it compiles without any error. Change-Id: Id63c52ffa2d111bd1f7c51831aa7087bef6006d9 Signed-off-by: Sowmya Aralguppe Reviewed-on: https://review.coreboot.org/c/coreboot/+/88102 Tested-by: build bot (Jenkins) Reviewed-by: Avi Uday --- .../google/ocelot/variants/ocelot/gpio.c | 568 +++++++++--------- 1 file changed, 289 insertions(+), 279 deletions(-) diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c index 58f1cb256e..6b11af063e 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/gpio.c +++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c @@ -7,382 +7,392 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { - /* GPP_A00: ESPI_ASOC_IO0_R */ - PAD_CFG_NF(GPP_A00, NONE, DEEP, NF1), - /* GPP_A01: ESPI_SOC_IO1_R */ - PAD_CFG_NF(GPP_A01, NONE, DEEP, NF1), - /* GPP_A02: ESPI_SOC_IO2_R */ - PAD_CFG_NF(GPP_A02, NONE, DEEP, NF1), - /* GPP_A03: ESPI_SOC_IO3_R */ - PAD_CFG_NF(GPP_A03, NONE, DEEP, NF1), - /* GPP_A04: ESPI_SOC_CS_R_L */ - PAD_CFG_NF(GPP_A04, NONE, DEEP, NF1), - /* GPP_A05: ESPI_SOC_CLK_R */ - PAD_CFG_NF(GPP_A05, NONE, DEEP, NF1), - /* GPP_A06: ESPI_SOC_RST_L # */ - PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), - /* GPP_A08: SSD_PERST_L # */ + /* GPP_A */ + /* GPP_A00: ESPI_IO0_AIC */ + /* GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */ + + /* GPP_A01: ESPI_IO1_AIC */ + /* GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */ + + /* GPP_A02: ESPI_IO2_AIC */ + /* GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */ + + /* GPP_A03: ESPI_IO3_AIC */ + /* GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */ + + /* GPP_A04: ESPI_CS0_AIC_N */ + /* GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */ + + /* GPP_A05: ESPI_CLK_AIC */ + /* GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */ + + /* GPP_A06: ESPI_RST_AIC_N */ + /* GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */ + + /* GPP_A08: M2_GEN4_SSD_RESET_N */ PAD_CFG_GPO(GPP_A08, 1, PLTRST), - /* GPP_A09: WWAN_EN */ - PAD_CFG_GPO(GPP_A09, 0, PLTRST), - /* GPP_A10: WWAN_RF_DISABLE_ODL */ + /* GPP_A09: M.2_WWAN_FCP_OFF_N */ + PAD_CFG_GPO(GPP_A09, 1, PLTRST), + /* GPP_A10: WWAN_DISABLE_N */ PAD_CFG_GPO(GPP_A10, 1, PLTRST), - /* GPP_A11: WLAN_PERST_L */ + /* GPP_A11: WLAN_RST_N */ PAD_CFG_GPO(GPP_A11, 1, PLTRST), - /* GPP_A12: WLAN_PCIE_WAKE_ODL */ + /* GPP_A12: WIFI_WAKE_N */ PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL), - /* GPP_A13: NC */ - PAD_NC(GPP_A13, NONE), - /* GPP_A15: EN_SPK_PA */ + /* GPP_A13: PCIE_LNK_DOWN */ + PAD_CFG_NF_OWNERSHIP(GPP_A13, NONE, DEEP, NF2, ACPI), + /* GPP_A15: CODEC_GPIO_EN */ PAD_CFG_GPO(GPP_A15, 1, DEEP), - /* GPP_B00: PMC_I2C_PD_SCL */ + /* GPP_B */ + /* GPP_B00: USBC_SML_CLK_PD */ PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1), - /* GPP_B01: PMC_I2C_PD_SDA */ + /* GPP_B01: USBC_SML_DATA_PD */ PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1), - /* GPP_B02: SOC_I2C_AUDIO_SDA */ - PAD_CFG_NF(GPP_B02, NONE, DEEP, NF8), - /* GPP_B03: SOC_I2C_AUDIO_SCL */ - PAD_CFG_NF(GPP_B03, NONE, DEEP, NF8), - /* GPP_B04: GPP_B04_STRAP */ - PAD_NC(GPP_B04, NONE), - /* GPP_B05: EC_ISH_INT_ODL */ - PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4), - /* GPP_B06: MEM_STRAP_2 */ - PAD_CFG_GPI(GPP_B06, NONE, DEEP), - /* GPP_B07: WWAN_SAR_DETECT_ODL */ - /* FIXME */ - PAD_CFG_GPI(GPP_B07, NONE, DEEP), - /* GPP_B08: MEM_STRAP_3 */ - PAD_CFG_GPI(GPP_B08, NONE, DEEP), - /* GPP_B09: BT_DISABLE_L */ - PAD_CFG_GPO(GPP_B09, 1, PLTRST), + /* GPP_B02: ISH_I2C0_SDA_SNSR_HDR */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3), + /* GPP_B03: ISH_I2C0_SCL_SNSR_HDR */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3), + /* GPP_B04: ISH_GP_0_SNSR_HDR */ + PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4), + /* GPP_B06: SOC_PDB_CTRL */ + PAD_CFG_GPO(GPP_B06, 0, DEEP), + /* GPP_B07: SLATEMODE_HALLOUT_SNSR_R */ + PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4), + /* GPP_B08: ISH_GP_4_SNSR_HDR */ + PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4), + /* GPP_B09: BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_B09, 1, DEEP), /* GPP_B10: NC */ PAD_NC(GPP_B10, NONE), - /* GPP_B12: SLR_SO_R_L */ + /* GPP_B12: PM_SLP_S0_N */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - /* GPP_B13: PLT_RST_L */ + /* GPP_B13: PLT_RST_N */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - /* GPP_B14: HDMI_HPD_STRAP */ + /* GPP_B14: GPP_B14_DDSP_HPDB */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), - /* GPP_B16: NC */ - PAD_NC(GPP_B16, NONE), - /* GPP_B17: GSC_SOC_INT_ODL */ - PAD_CFG_GPI(GPP_B17, NONE, DEEP), - /* GPP_B18: ISH_I2C_SENSOR_SDA */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* GPP_B19: ISH_I2C_SENSOR_SCL */ - PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), - /* GPP_B20: WWAN_RST_ODL */ + /* GPP_B16: COINLESS_MODE_SELECT */ + PAD_CFG_GPI(GPP_B16, NONE, DEEP), + /* GPP_B17: SPI_TPM_INT_N */ + PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1), + /* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1), + /* GPP_B20: WWAN_RST_N */ PAD_CFG_GPO(GPP_B20, 1, PLTRST), - /* GPP_B21: USB_RT_FORCE_PWR */ - /* FIXME */ + /* GPP_B21: TCP_RETIMER_FORCE_PWR */ PAD_CFG_GPO(GPP_B21, 0, DEEP), - /* GPP_B22: ISH_ACCEL_DB_INT_L */ + /* GPP_B22: ISH_GP_5_SNSR_HDR */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4), - /* GPP_B23: GPP_B23_STRAP */ - PAD_NC(GPP_B23, NONE), - /* GPP_B24: EC_SOC_INT_ODL */ - PAD_CFG_GPI(GPP_B24, NONE, DEEP), - /* GPP_B25: GPP_B23_STRAP */ + /* GPP_B23: ISH_GP_6_SNSR_HDR */ + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4), + /* GPP_B24: ESPI_ALERT0_EC_R_N */ + PAD_NC(GPP_B24, NONE), + /* GPP_B25: None */ PAD_NC(GPP_B25, NONE), - /* GPP_C00: NC */ - PAD_NC(GPP_C00, NONE), - /* GPP_C01: NC */ - PAD_NC(GPP_C01, NONE), - /* GPP_C02: GPP_C02_STRAP */ + /* GPP_C */ + /* GPP_C00: SPD_SMB_CLK */ + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), + /* GPP_C01: SPD_SMB_DATA */ + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), + /* GPP_C02: NC */ PAD_NC(GPP_C02, NONE), - /* GPP_C03: TP_SMB_SML0_CLK */ + /* GPP_C03: TCP_LAN_SML0_SCL_R */ PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), - /* GPP_C04: TP_SMB_SML0_DAT */ + /* GPP_C04: TCP_LAN_SML0_SDA_R */ PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), - /* GPP_C05: GPP_C05_STRAP */ + /* GPP_C05: NC */ PAD_NC(GPP_C05, NONE), /* GPP_C06: NC */ PAD_NC(GPP_C06, NONE), /* GPP_C07: NC */ PAD_NC(GPP_C07, NONE), - /* GPP_C08: ASLP_S0_GATE_R */ - /* FIXME */ - PAD_CFG_GPO(GPP_C08, 0, DEEP), - /* GPP_C09: WLAN_PCIE_CLKREQ_ODL */ + /* GPP_C08: PM_SLP_S0_N_GPP_CNTRL */ + PAD_CFG_GPO(GPP_C08, 1, PLTRST), + /* GPP_C09: CLKREQ0_X1_GEN4_M2_WLAN_N */ PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), - /* GPP_C10: WIFI_DISABLE_L */ - PAD_CFG_GPO(GPP_C10, 1, PLTRST), - /* GPP_C11: OPT_PCIE_CLKREQ_ODL */ + /* GPP_C10: WIFI_RF_KILL_N */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* GPP_C11: CLKREQ2_X4_GEN4_DT_CEM_SLOT1_N */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), - /* GPP_C12: SSD_PCIE_CLKREQ_ODL */ + /* GPP_C12: CLKREQ3_X4_GEN4_M2_SSD_N */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), - /* GPP_C13: NC */ - PAD_NC(GPP_C13, NONE), - /* GPP_C14: NC */ - PAD_NC(GPP_C14, NONE), - /* GPP_C15: SOC_FP_RST_STRAP_L */ - PAD_CFG_GPO(GPP_C15, 1, DEEP), - /* GPP_C16: USB_C0_LSX_TX */ + /* GPP_C13: CLKREQ4_X4_GEN4_DT_CEM_SLOT2_N */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* GPP_C14: CLKREQ5_X1_GEN1_GBE_LAN_N */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + /* GPP_C15: FPS_RST_N */ + PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG), + /* GPP_C16: MOD_TCSS1_LS_TX_DDC_SCL */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - /* GPP_C17: USB_C0_LSX_RX */ + /* GPP_C17: MOD_TCSS1_LS_RX_DDC_SDA */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* GPP_C18: USB_C1_LSX_TX */ + /* GPP_C18: MOD_TCSS2_LS_TX_DDC_SCL */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* GPP_C19: USB_C1_LSX_TX */ + /* GPP_C19: MOD_TCSS2_LS_RX_DDC_SDA */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* GPP_C20: USB_C1_LSX_RX */ - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - /* GPP_C22: DDIB_HDMI_CTRLCLK */ + /* GPP_C22: DDPB_HDMI_CTRLCLK */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), - /* GPP_C23: DDIB_HDMI_CTRLDATA */ + /* GPP_C23: DDPB_HDMI_CTRLDATA */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), - /* GPP_D01: NC */ - PAD_NC(GPP_D01, NONE), + /* GPP_D */ + /* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */ + PAD_CFG_GPO(GPP_D01, 1, DEEP), /* GPP_D02: SOC_WP_OD */ - PAD_CFG_GPI(GPP_D02, NONE, DEEP), - /* GPP_D03: OPT_PCIE_WAKE_ODL */ + PAD_CFG_GPO(GPP_D02, 0, DEEP), + /* GPP_D03: X4_SLOT_WAKE_N */ PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL), - /* GPP_D05: UART_ISH_RX_DBG_TX */ + /* GPP_D05: ISH_UART0_ECAIC_RXD */ PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2), - /* GPP_D06: UART_ISH_TX_DBG_RX */ + /* GPP_D06: ISH_UART0_ECAIC_TXD */ PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2), - /* GPP_D07: NC */ - PAD_NC(GPP_D07, NONE), - /* GPP_D08: NC */ - PAD_NC(GPP_D08, NONE), - /* GPP_D09: I2S0_MCLK_R */ - PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2), - /* GPP_D10: HDA_BCLK_I2S0_SCLK */ + /* GPP_D07: ISH_UART0_RTS_N_SNSR_HDR */ + PAD_CFG_NF(GPP_D07, NONE, DEEP, NF3), + /* GPP_D08: ISH_UART0_CTS_N_SNSR_HDR */ + PAD_CFG_NF(GPP_D08, NONE, DEEP, NF3), + /* GPP_D09: I2S_MCLK_HDR */ + PAD_CFG_NF(GPP_D09, NONE, DEEP, NF1), + /* GPP_D10: HDA_BCLK (HDR) */ PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), - /* GPP_D11: HDA_SYNC_I2S0_SFRM */ + /* GPP_D11: HDA_SYNC (HDR) */ PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1), - /* GPP_D12: HDA_SD0_I2S0_TXD_STRAP */ + /* GPP_D12: HDA_SDO (HDR) */ PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), - /* GPP_D13: HDA_SDI0_I2S0_RDX */ + /* GPP_D13: HDA_SDI0 (HDR) */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), - /* GPP_D16: NC */ - PAD_NC(GPP_D16, NONE), - /* GPP_D17: NC */ - PAD_NC(GPP_D17, NONE), - /* GPP_D19: SOC_TCHSCR_REPORT_EN */ - PAD_CFG_GPO(GPP_D18, 0, DEEP), - /* GPP_D21: SOC_UFS_REFCLK */ + /* GPP_D16: HDA_RST_N (HDR) */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), + /* GPP_D17: HDA_SDI1 (HDR) */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* GPP_D19: NC */ + PAD_NC(GPP_D19, NONE), + /* GPP_D21: GPP_D21_UFS_REFCLK_R */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), - /* GPP_E01: EN_WWAN_PWR */ - PAD_CFG_GPO(GPP_E01, 1, PLTRST), + /* GPP_E */ + /* GPP_E01: PM_SLP_DRAM_N */ + PAD_CFG_NF(GPP_E01, NONE, DEEP, NF2), /* GPP_E02: NC */ PAD_NC(GPP_E02, NONE), - /* GPP_E03: OPT_PERST_L */ - PAD_CFG_GPO(GPP_E03, 1, DEEP), - /* GPP_E05: EN_PWR_FP */ - PAD_CFG_GPO(GPP_E05, 0, PLTRST), - /* GPP_E06: GPP_E06_STRAP */ - PAD_NC(GPP_E06, NONE), - /* GPP_E07: NC */ - PAD_NC(GPP_E07, NONE), - /* GPP_E08: NC */ - PAD_NC(GPP_E08, NONE), - /* GPP_E09: USB_A_OC_ODL */ + /* GPP_E03: X4_DT_PCIE_RST_N */ + PAD_CFG_GPO(GPP_E03, 1, PLTRST), + /* GPP_E05: GPP_E5_FPS_PWREN */ + PAD_CFG_GPO(GPP_E05, 1, DEEP), + /* GPP_E06: GPP_E6_PEN_DETECT */ + PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, LEVEL, ACPI), + /* GPP_E07: LAN_GPIO_RST_N */ + PAD_CFG_GPO(GPP_E07, 1, PLTRST), + /* GPP_E08: EC_SOC_INT_ODL */ + PAD_CFG_GPI(GPP_E08, NONE, DEEP), + /* GPP_E09: USB_FP_CONN_1_CONN_2_OC0_N */ PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1), - /* GPP_E10: SD_PE_PRSNT_L */ + /* GPP_E10: M2_UFS_DET_SEL_N */ PAD_CFG_GPI(GPP_E10, NONE, DEEP), - /* GPP_E11: SPI_SOC_CLK_FP_R */ - PAD_CFG_NF(GPP_E11, NONE, DEEP, NF5), - /* GPP_E12: SOC_I2C_TCHPAD_SCL */ - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), - /* GPP_E13: SOC_I2C_TCHPAD_SCL */ - PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), - /* GPP_E14: NC */ - PAD_NC(GPP_E14, NONE), - /* GPP_E15: NC */ - PAD_NC(GPP_E15, NONE), - /* GPP_E16: NC */ - PAD_NC(GPP_E16, NONE), - /* GPP_E17: SPI_SOC_CS_FP_R_L */ + /* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3), + /* GPP_E12: THC_I2C0_SCL_TCH_PNL1 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3), + /* GPP_E13: THC_I2C0_SDA_TCH_PNL1 */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3), + /* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3), + /* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3), + /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */ + PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1), + /* GPP_E17: GPP_E17_GSPI0A_CS0 */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5), - /* GPP_E18: SOC_TCHPAD_INT_ODL */ + /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), - /* GPP_E19: FP_SOC_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_E19, NONE, DEEP, LEVEL), - /* GPP_E20: SOC_FP_FW_UP */ - PAD_CFG_GPO(GPP_E20, 0, DEEP), - /* GPP_E21: PMC_I2C_PD_INT_ODL */ + /* GPP_E19: FPS_INT_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E19, NONE, PWROK, LEVEL, INVERT), + /* GPP_E20: FPS_FW_UPDATE */ + PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG), + /* GPP_E21: I2C_PMC_PD_INT_N */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* GPP_E22: NC */ PAD_NC(GPP_E22, NONE), - /* GPP_F00: CNV_BRI_DT_R */ - PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), - /* GPP_F01: CNV_BRI_RSP */ - PAD_CFG_NF(GPP_F01, NONE, DEEP, NF1), - /* GPP_F02: WLAN_CNVI_RGI_DT_STRAP_R */ - PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), - /* GPP_F03: CNV_RGI_RSP */ - PAD_CFG_NF(GPP_F03, NONE, DEEP, NF1), - /* GPP_F04: CNV_RF_RST_L */ - PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), - /* GPP_F05: CNV_CLKREQ0 */ - PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), - /* GPP_F06: COEX3_WWAN_WLAN */ + /* GPP_F */ + /* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1), + /* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1), + /* GPP_F04: CNV_RF_RESET_R_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05: CRF_CLKREQ_R */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3), + /* GPP_F06: DISC_WLAN_WWAN_COEX3 */ PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), - /* GPP_F07: EN_PP3300_SD */ - PAD_CFG_GPO(GPP_F07, 1, PLTRST), - /* GPP_F08: EN_PP3300_TCHSCR */ + /* GPP_F07: FUSA_DIAGTEST_EN_HDR */ + PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2), + /* GPP_F08: TCH_PNL1_PWR_EN */ PAD_CFG_GPO(GPP_F08, 1, PLTRST), - /* GPP_F09: SOC_UFS_RST_L */ - PAD_CFG_GPO(GPP_F09, 0, PLTRST), - /* GPP_F10: ISH_ACCEL_MB_INT_L */ - PAD_CFG_NF(GPP_F10, NONE, PLTRST, NF8), - /* GPP_F11: SPI_TCHSCR_CLK */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF3), - /* GPP_F12: SPI_I2C_TCHSCR_MOSI_SCL */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF3), - /* GPP_F13: SPI_I2C_TCHSCR_MISO_SDA */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF3), - /* GPP_F14: SPI_SOC_D0_FP_D1_R */ + /* GPP_F09: M2_UFS_RST_N */ + PAD_CFG_GPO(GPP_F09, 1, DEEP), + /* GPP_F10: X4_PCIE_SLOT1_PWR_EN */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + /* GPP_F11: THC1_SPI2_CLK_TCH_PNL2 */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF11), + /* GPP_F12: THC_I2C1_SCL_TCH_PAD */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), + /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), + /* GPP_F14: GPP_F14_GPSI0A_MOSI */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8), - /* GPP_F15: SPI_SOC_D1_FP_D0 */ + /* GPP_F15: GPP_F15_GSPI0A_MISO */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8), - /* GPP_F16: THCSCR_RST_L */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF3), - /* GPP_F17: SPI_THCSCR_CS_L */ - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF3), - /* GPP_F18: TCHSCR_INT_ODL */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF3), - /* GPP_F19: GPP_F19_STRAP */ + /* GPP_F16: GPP_F16_GSPI0A_CLK */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8), + /* GPP_F17: CODEC_IRQ_HDR */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), + /* GPP_F18: TCH_PAD_INT_N */ + PAD_CFG_GPI_APIC_DRIVER(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* GPP_F19: NC */ PAD_NC(GPP_F19, NONE), - /* GPP_F20: EC_SOC_REC_SWITCH_ODL */ - PAD_CFG_GPO(GPP_F20, 0, PLTRST), - /* GPP_F22: NC */ - PAD_NC(GPP_F22, NONE), - /* GPP_F23: TP_ISH_LID_OPEN */ - PAD_CFG_NF(GPP_F23, NONE, PLTRST, NF8), + /* GPP_F20: CSE_EARLY_SW */ + PAD_CFG_GPI(GPP_F20, NONE, DEEP), + /* GPP_F22: THC1_SPI2_DSYNC */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3), + /* GPP_F23: SMC_LID */ + PAD_CFG_GPI_SCI_LOW(GPP_F23, NONE, DEEP, LEVEL), - /* GPP_H02: GPP_H02_STRAP */ - PAD_NC(GPP_H02, NONE), - /* GPP_H03: NC */ - PAD_NC(GPP_H03, NONE), - /* GPP_H04: COEX1_SOC_RX_WWAN_RX_WLAN_TX */ - PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), - /* GPP_H05: COEX1_SOC_TX_WWAN_TX_WLAN_RX */ - PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), - /* GPP_H06: UART_SOC_RX_FP_TX */ - PAD_CFG_NF(GPP_H06, NONE, DEEP, NF2), - /* GPP_H07: UART_SOC_TX_FP_RX */ - PAD_CFG_NF(GPP_H07, NONE, DEEP, NF2), - /* GPP_H08: UART_SOC_RX_DBG_TX */ + /* GPP_H */ + /* GPP_H00: NC */ + PAD_NC(GPP_H00, NONE), + /* GPP_H01: M2_UFS_SLP_N */ + PAD_CFG_GPO(GPP_H01, 1, DEEP), + /* GPP_H02: DEBUG_TRACE_PNP */ + PAD_CFG_GPO(GPP_H02, 1, PLTRST), + /* GPP_H03: MIC MUTE */ + PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1), + /* GPP_H04: CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1), + /* GPP_H05: CNV_MFUART2_TXD */ + PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1), + /* GPP_H06: I2C3_SCL_AUDIO_HDR */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), + /* GPP_H07: I2C3_SDA_AUDIO_HDR */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_H08: SOC_BIOS_LOG_TTK_UART_RX */ PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), - /* GPP_H09: UART_SOC_TX_DBG_RX */ + /* GPP_H09: SOC_BIOS_LOG_TTK_UART_TX */ PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), - /* GPP_H10: TP_ISH_TABLET_MODE */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF8), - /* GPP_H11: TP_ISH_GP11 */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF8), - /* GPP_H13: TP_PROC_C10_GATE_L */ + /* GPP_H10: UART0_BUF_RTS */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + /* GPP_H11: UART0_BUF_CTS */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + /* GPP_H13: CPU_C10_GATE_N_R */ PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), - /* GPP_H14: NC */ - PAD_NC(GPP_H14, NONE), - /* GPP_H15: NC */ - PAD_NC(GPP_H15, NONE), - /* GPP_H17: HP_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_H17, NONE, DEEP, LEVEL), - /* GPP_H18: EN_PP3300_SSD */ + /* GPP_H14: ISH_I3C1_SDA_SNSR_HDR */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_H14, NONE, DEEP, NF4), + /* GPP_H15: ISH_I3C1_SCL_SNSR_HDR */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_H15, NONE, DEEP, NF4), + /* GPP_H17: MIC MUTE LED */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* GPP_H18: GEN4_SSD_PWREN */ PAD_CFG_GPO(GPP_H18, 1, DEEP), - /* GPP_H19: TP_SOC_I2C0_I3C0SDA */ - PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), - /* GPP_H20: TP_SOC_I2C0_I3C0SCL */ - PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), - /* GPP_H21: SOC_I2C_GSC_SDA */ + /* GPP_H19: I3C0_SDA_HDR */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2), + /* GPP_H20: I3C0_SCL_HDR */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2), + /* GPP_H21: I2C1_SDA_TTK_CHROME */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), - /* GPP_H22: SOC_I2C_GSC_SCL */ + /* GPP_H22: I2C1_SCL_TTK_CHROME */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), - /* GPP_H23: MEM_STRAP_0 */ - PAD_CFG_GPI(GPP_H23, NONE, DEEP), - /* GPP_H24: MEM_STRAP_1 */ - PAD_CFG_GPI(GPP_H24, NONE, DEEP), + /* GPP_H23: TP */ + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), + /* GPP_H24: TP */ + PAD_CFG_NF(GPP_H24, NONE, DEEP, NF1), - /* GPP_S00: SDW3_CLK_I2S1_TXD */ + /* GPP_S */ + /* GPP_S00: SNDW3_CLK_CODEC (HDR) */ PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), - /* GPP_S01: SDW3_DAT0 */ + /* GPP_S01: SNDW3_DATA0_CODEC (HDR) */ PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), - /* GPP_S02: SDW3_DAT1_I2S1_SCLK */ + /* GPP_S02: SNDW3_DATA1_CODEC (HDR) */ PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1), - /* GPP_S03: SDW3_DAT2_I2S1_SFRM */ + /* GPP_S03: SNDW3_DATA2_CODEC (HDR) */ PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1), - /* GPP_S04: DMIC_CLK0_R */ + /* GPP_S04: DMIC0_CLK (HDR) */ PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5), - /* GPP_S05: DMIC_DATA0_EDP */ + /* GPP_S05: DMIC0_DATA (HDR) */ PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5), - /* GPP_S06: NC */ - PAD_NC(GPP_S06, NONE), - /* GPP_S07: NC */ - PAD_NC(GPP_S07, NONE), + /* GPP_S06: DMIC1_CLK (HDR) */ + PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5), + /* GPP_S07: DMIC1_DATA (HDR) */ + PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5), - /* GPP_V00: BATLOW_L */ + /* GPP_V */ + /* GPP_V00: PM_BATLOW_N */ PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), - /* GPP_V01: EC_AC_PRESENT_OD */ + /* GPP_V01: BC_ACOK_MCP */ PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), - /* GPP_V02: EC_SOC_WAKE_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_V02, NONE, PLTRST, LEVEL, INVERT), - /* GPP_V03: EC_SOC_PWR_BTN_ODL */ + /* GPP_V02: LANWAKE_N_R */ + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), + /* GPP_V03: PWRBTN_MCP_N */ PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), - /* GPP_V04: SLP_S3_L */ + /* GPP_V04: PM_SLP_S3_N */ PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), - /* GPP_V05: SLP_S4_L */ + /* GPP_V05: PM_SLP_S4_N */ PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), - /* GPP_V06: TP_SLP_A_L */ - PAD_NC(GPP_V06, NONE), - /* GPP_V07: SOC_WLAN_SUSCLK */ + /* GPP_V06: PM_SLP_A_N */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), + /* GPP_V07: M.2_BTWIFI_SUS_CLK_LS */ PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1), - /* GPP_V08: NC */ - PAD_NC(GPP_V08, NONE), - /* GPP_V09: SLP_S5_L */ + /* GPP_V08: SLP_WLAN_N */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), + /* GPP_V09: PM_SLP_S5_N */ PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), - /* GPP_V10: NC */ - PAD_NC(GPP_V10, NONE), - /* GPP_V11: TP_SLP_LAN_L */ - PAD_NC(GPP_V11, NONE), - /* GPP_V12: PCH_WAKE_L */ + /* GPP_V10: LANPHYPC_R_N */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), + /* GPP_V11: PM_SLP_LAN_N */ + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), + /* GPP_V12: WAKE_N */ PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), - /* GPP_V16: EN_VCCST */ + /* GPP_V13: GPP_V13_CATERR_N */ + PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1), + /* GPP_V14: GPP_V14_FORCEPR_N */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + /* GPP_V15: GPP_V15_THERMTRIP_N */ + PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1), + /* GPP_V16: GPP_V16_VCCST_EN */ PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /* GPP_B05: EC_ISH_INT_ODL */ - PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4), - /* GPP_B17: GSC_SOC_INT_ODL */ - PAD_CFG_GPI(GPP_B17, NONE, DEEP), - /* GPP_B24: EC_SOC_INT_ODL */ - PAD_CFG_GPI(GPP_B24, NONE, DEEP), - - /* GPP_D05: UART_ISH_RX_DBG_TX */ - PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2), - /* GPP_D06: UART_ISH_TX_DBG_RX */ - PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2), - - /* GPP_F20: EC_SOC_REC_SWITCH_ODL */ - PAD_CFG_GPO(GPP_F20, 0, PLTRST), - - /* GPP_H06: UART_SOC_RX_FP_TX */ - PAD_CFG_NF(GPP_H06, NONE, DEEP, NF2), - /* GPP_H07: UART_SOC_TX_FP_RX */ - PAD_CFG_NF(GPP_H07, NONE, DEEP, NF2), - /* GPP_H08: UART_SOC_RX_DBG_TX */ + /* GPP_B17: SPI_TPM_INT_N */ + PAD_CFG_GPI_APIC(GPP_B17, NONE, DEEP, LEVEL, INVERT), + /* GPP_H06: I2C3_SDA_PSS */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), + /* GPP_H07: I2C3_SCL_PSS */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_H08: SOC_BIOS_LOG_TTK_UART_RX */ PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), - /* GPP_H09: UART_SOC_TX_DBG_RX */ + /* GPP_H09: SOC_BIOS_LOG_TTK_UART_TX */ PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), - /* GPP_H21: SOC_I2C_GSC_SDA */ + /* GPP_H21: I2C1_SDA_TTK_CHROME */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), - /* GPP_H22: SOC_I2C_GSC_SCL */ + /* GPP_H22: I2C1_SCL_TTK_CHROME */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), }; /* Pad configuration in romstage */ static const struct pad_config romstage_gpio_table[] = { - /* GPP_A08: SSD_PERST_L */ - PAD_CFG_GPO(GPP_A08, 0, PLTRST), + /* GPP_C00: SPD_SMB_CLK */ + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), + /* GPP_C01: SPD_SMB_DATA */ + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), + /* GPP_C15: FPS_RST_N */ + PAD_CFG_GPO(GPP_C15, 0, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num)