diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index de731f3048..92aec1173f 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -358,6 +358,7 @@ StarBook Mk V StarBook Mk VI StarBook Mk VII (N200) StarBook Mk VII (165H) +StarBook Horizon Byte Mk II StarFighter Mk I StarFighter Mk II diff --git a/Documentation/mainboard/starlabs/adl_horizon.md b/Documentation/mainboard/starlabs/adl_horizon.md new file mode 100644 index 0000000000..4d81b7f9fc --- /dev/null +++ b/Documentation/mainboard/starlabs/adl_horizon.md @@ -0,0 +1,86 @@ +# StarBook Mk V + +## Specs + +- CPU (full processor specs available at ) + - Intel N305 (Alder Lake) +- EC + - ITE IT5570E + - Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys + - Battery + - USB-C PD Charger + - Suspend / resume +- GPU + - Intel® Iris® Xe Graphics + - GOP driver is recommended, VBT is provided + - eDP 13.4-inch 2520x1680 LCD + - HDMI video + - USB-C DisplayPort video +- Memory + - 32GB LPDD% on-board memory +- Networking + - AX210 2230 WiFi / Bluetooth +- Sound + - Realtek ALC269-VB6 + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - HDMI audio + - USB-C DisplayPort audio +- Storage + - M.2 PCIe SSD +- USB + - 1920x1080 CCD camera + - USB 3.1 Gen 2 (left) + - USB 3.1 Gen 2 (right) + - USB 3.1 Gen 2 Type-A (right) + +## Building coreboot + +Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_adl_horizon` as config file. + +### Preliminaries + +Prior to building coreboot the following files are required: +* Intel Flash Descriptor file (descriptor.bin) +* Intel Management Engine firmware (me.bin) +* ITE Embedded Controller firmware (ec.bin) + +The files listed below are optional: +- Splash screen image in Windows 3.1 BMP format (Logo.bmp) + +These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. + +### Build + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_adl_horizon_n +make +``` + +## Flashing coreboot + +```{eval-rst} ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | W25Q256.V | ++---------------------+------------+ +| Size | 32 MiB | ++---------------------+------------+ +| Package | WSON-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | yes | ++---------------------+------------+ +``` + +Please see [here](common/flashing.md) for instructions on how to flash with fwupd. diff --git a/src/mainboard/starlabs/adl/Kconfig b/src/mainboard/starlabs/adl/Kconfig new file mode 100644 index 0000000000..adfa25bb8d --- /dev/null +++ b/src/mainboard/starlabs/adl/Kconfig @@ -0,0 +1,117 @@ +config BOARD_STARLABS_ADL_SERIES + def_bool n + select AZALIA_USE_LEGACY_VERB_TABLE + select CSE_DEFAULT_CFR_OPTION_STATE_DISABLED + select DRIVERS_EFI_VARIABLE_STORE + select DRIVERS_GFX_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_INTEL_PMC + select DRIVERS_OPTION_CFR_ENABLED + select EC_STARLABS_MERLIN + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_HDA_DMIC + select HAVE_OPTION_TABLE + select HAVE_SPD_IN_CBFS + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_TPM2 + select MEMORY_MAPPED_TPM + select NO_UART_ON_SUPERIO + select PMC_IPC_ACPI_INTERFACE + select SOC_INTEL_ALDERLAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_COMMON_BLOCK_TCSS + select SOC_INTEL_CRASHLOG + select SPD_READ_BY_WORD + select SPI_FLASH_WINBOND + select SYSTEM_TYPE_LAPTOP + select TPM2 + select TPM_MEASURED_BOOT + select VALIDATE_INTEL_DESCRIPTOR + +config BOARD_STARLABS_ADL_HORIZON + select BOARD_ROMSIZE_KB_16384 + select BOARD_STARLABS_ADL_SERIES + select SOC_INTEL_ALDERLAKE_PCH_N + +if BOARD_STARLABS_ADL_HORIZON + +config CCD_PORT + int + default 4 + +config CONSOLE_SERIAL + default n if !EDK2_DEBUG + +config D3COLD_SUPPORT + default n + +config DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + default 512 + +config EDK2_BOOTSPLASH_FILE + string + default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" + +config EC_STARLABS_BATTERY_MODEL + default "U5266122PV-2S1P" + +config EC_STARLABS_BATTERY_TYPE + default "LION" + +config EC_STARLABS_BATTERY_OEM + default "Shenzhen Utility Energy Co., Ltd" + +config EC_STARLABS_ITE_BIN_PATH + string + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin" + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" + +config IFD_BIN_PATH + string + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashdescriptor.bin" + +config MAINBOARD_DIR + default "starlabs/adl" + +config MAINBOARD_FAMILY + string + default "HZ" + +config MAINBOARD_PART_NUMBER + default "StarBook Horizon" + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "StarBook Horizon" + +config ME_BIN_PATH + string + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/intel_me.bin" + +config POWER_STATE_DEFAULT_ON_AFTER_FAILURE + default n + +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n + +config TPM_PIRQ + depends on MAINBOARD_HAS_TPM2 + default 0x28 + +config UART_FOR_CONSOLE + default 0 + +config USE_PM_ACPI_TIMER + default n + +config VARIANT_DIR + default "hz" + +endif diff --git a/src/mainboard/starlabs/adl/Kconfig.name b/src/mainboard/starlabs/adl/Kconfig.name new file mode 100644 index 0000000000..e9af44560e --- /dev/null +++ b/src/mainboard/starlabs/adl/Kconfig.name @@ -0,0 +1,4 @@ +comment "Star Labs StarLite Series" + +config BOARD_STARLABS_ADL_HORIZON + bool "Star Labs StarBook Horizon (N305)" diff --git a/src/mainboard/starlabs/adl/Makefile.mk b/src/mainboard/starlabs/adl/Makefile.mk new file mode 100644 index 0000000000..ad15bbd510 --- /dev/null +++ b/src/mainboard/starlabs/adl/Makefile.mk @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += ./spd +subdirs-y += variants/$(VARIANT_DIR) + +bootblock-y += bootblock.c + +ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c +ramstage-y += mainboard.c diff --git a/src/mainboard/starlabs/adl/acpi/ec.asl b/src/mainboard/starlabs/adl/acpi/ec.asl new file mode 100644 index 0000000000..853b0877b3 --- /dev/null +++ b/src/mainboard/starlabs/adl/acpi/ec.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/starlabs/adl/acpi/mainboard.asl b/src/mainboard/starlabs/adl/acpi/mainboard.asl new file mode 100644 index 0000000000..34b90af325 --- /dev/null +++ b/src/mainboard/starlabs/adl/acpi/mainboard.asl @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB) { + #include "sleep.asl" +} diff --git a/src/mainboard/starlabs/adl/acpi/sleep.asl b/src/mainboard/starlabs/adl/acpi/sleep.asl new file mode 100644 index 0000000000..7ed74e3514 --- /dev/null +++ b/src/mainboard/starlabs/adl/acpi/sleep.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (MPTS, 1, NotSerialized) +{ + RPTS (Arg0) +} + +Method (MWAK, 1, NotSerialized) +{ + RWAK (Arg0) +} diff --git a/src/mainboard/starlabs/adl/acpi/superio.asl b/src/mainboard/starlabs/adl/acpi/superio.asl new file mode 100644 index 0000000000..853b0877b3 --- /dev/null +++ b/src/mainboard/starlabs/adl/acpi/superio.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/starlabs/adl/board_info.txt b/src/mainboard/starlabs/adl/board_info.txt new file mode 100644 index 0000000000..5416db044b --- /dev/null +++ b/src/mainboard/starlabs/adl/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Star Labs +Board name: StarBook Horizon +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/starlabs/adl/bootblock.c b/src/mainboard/starlabs/adl/bootblock.c new file mode 100644 index 0000000000..ca48bb1ab2 --- /dev/null +++ b/src/mainboard/starlabs/adl/bootblock.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/starlabs/adl/cfr.c b/src/mainboard/starlabs/adl/cfr.c new file mode 100644 index 0000000000..4f920a69f6 --- /dev/null +++ b/src/mainboard/starlabs/adl/cfr.c @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +static struct sm_obj_form performance_group = { + .ui_name = "Performance", + .obj_list = (const struct sm_object *[]) { + &fan_mode, + &memory_speed, + &power_profile, + NULL + }, +}; + +static struct sm_obj_form processor_group = { + .ui_name = "Processor", + .obj_list = (const struct sm_object *[]) { + &me_state, + &me_state_counter, + &s0ix_enable, + &vtd, + NULL + }, +}; + +static struct sm_obj_form power_group = { + .ui_name = "Power", + .obj_list = (const struct sm_object *[]) { + &max_charge, + &charging_speed, + &power_led, + &charge_led, + &power_on_after_fail_bool, + NULL + }, +}; + +static struct sm_obj_form keyboard_group = { + .ui_name = "Keyboard", + .obj_list = (const struct sm_object *[]) { + &kbl_timeout, + &fn_ctrl_swap, + NULL + }, +}; + +static struct sm_obj_form devices_group = { + .ui_name = "Devices", + .obj_list = (const struct sm_object *[]) { + &bluetooth, + &display_native_res, + &gna, + &lid_switch, + µphone, + &webcam, + &wifi, + NULL + }, +}; + +static struct sm_obj_form security_group = { + .ui_name = "Security", + .obj_list = (const struct sm_object *[]) { + &bios_lock, + &intel_tme, + NULL + }, +}; + +static struct sm_obj_form pci_group = { + .ui_name = "PCI", + .obj_list = (const struct sm_object *[]) { + &pciexp_clk_pm, + &pciexp_aspm, + &pciexp_l1ss, + NULL + }, +}; + +static struct sm_obj_form coreboot_group = { + .ui_name = "coreboot", + .obj_list = (const struct sm_object *[]) { + &debug_level, + NULL + }, +}; + +static struct sm_obj_form *sm_root[] = { + &performance_group, + &processor_group, + &power_group, + &keyboard_group, + &devices_group, + &security_group, + &pci_group, + &coreboot_group, + NULL +}; + +void mb_cfr_setup_menu(struct lb_cfr *cfr_root) +{ + starlabs_cfr_register_overrides(); + cfr_write_setup_menu(cfr_root, sm_root); +} diff --git a/src/mainboard/starlabs/adl/cmos.default b/src/mainboard/starlabs/adl/cmos.default new file mode 100644 index 0000000000..49faae3e6a --- /dev/null +++ b/src/mainboard/starlabs/adl/cmos.default @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only +# Functions +fn_lock_state=0x1 +trackpad_state=0x1 +kbl_brightness=0x0 +kbl_state=0x1 diff --git a/src/mainboard/starlabs/adl/cmos.layout b/src/mainboard/starlabs/adl/cmos.layout new file mode 100644 index 0000000000..ebba7fbd5d --- /dev/null +++ b/src/mainboard/starlabs/adl/cmos.layout @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# Bank: 1 +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# coreboot config options: ramtop +304 80 h 0 ramtop + +# RTC_BOOT_BYTE (coreboot hardcoded) +388 4 h 0 reboot_counter + +# coreboot config options: cpu +#400 8 r 0 reserved for century byte + +# coreboot config options: check sums +984 16 h 0 check_sum + +# Bank: 2 +# embedded controller settings (outside the checksummed area) +1024 8 h 1 fn_lock_state +1032 8 h 1 trackpad_state +1040 8 h 2 kbl_brightness +1048 8 h 1 kbl_state + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Off +2 1 Low +2 2 High +2 3 On + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/starlabs/adl/dsdt.asl b/src/mainboard/starlabs/adl/dsdt.asl new file mode 100644 index 0000000000..b7783eae63 --- /dev/null +++ b/src/mainboard/starlabs/adl/dsdt.asl @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20220930 +) +{ + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + + #include + + #include + + /* PS/2 Keyboard */ + #include + } + + #include + + /* Star Labs EC */ + #include + + Scope (\_SB) + { + /* HID Driver */ + #include + + /* Suspend Methods */ + #include + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/starlabs/adl/include/variants.h b/src/mainboard/starlabs/adl/include/variants.h new file mode 100644 index 0000000000..c95d15bd72 --- /dev/null +++ b/src/mainboard/starlabs/adl/include/variants.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BASEBOARD_VARIANTS_H_ +#define _BASEBOARD_VARIANTS_H_ + +#include + +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. + */ +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +void devtree_update(void); + +#endif /* _BASEBOARD_VARIANTS_H_ */ diff --git a/src/mainboard/starlabs/adl/mainboard.c b/src/mainboard/starlabs/adl/mainboard.c new file mode 100644 index 0000000000..1d2fceae53 --- /dev/null +++ b/src/mainboard/starlabs/adl/mainboard.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static void init_mainboard(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); + + devtree_update(); +} + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; diff --git a/src/mainboard/starlabs/adl/spd/Makefile.mk b/src/mainboard/starlabs/adl/spd/Makefile.mk new file mode 100644 index 0000000000..f979c5a066 --- /dev/null +++ b/src/mainboard/starlabs/adl/spd/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +SPD_SOURCES = rs4g32l05d8fdb-5500 +SPD_SOURCES += rs4g32l05d8fdb-6400 +SPD_SOURCES += rs4g32l05d8fdb-7500 diff --git a/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-5500.spd.hex b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-5500.spd.hex new file mode 100644 index 0000000000..a52441a71b --- /dev/null +++ b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-5500.spd.hex @@ -0,0 +1,32 @@ +23 10 13 0E 16 2A 91 08 00 00 00 00 09 01 00 00 +00 00 0B 00 00 00 00 00 AE 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 4B 00 50 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-6400.spd.hex b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-6400.spd.hex new file mode 100644 index 0000000000..0969d01568 --- /dev/null +++ b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-6400.spd.hex @@ -0,0 +1,32 @@ +23 10 13 0E 16 2A 91 08 00 00 00 00 09 01 00 00 +00 00 0A 00 00 00 00 00 AA 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-7500.spd.hex b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-7500.spd.hex new file mode 100644 index 0000000000..c132efab8c --- /dev/null +++ b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-7500.spd.hex @@ -0,0 +1,32 @@ +23 10 13 0E 16 2A 91 08 00 00 00 00 09 01 00 00 +00 00 08 00 00 00 00 00 AA 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 46 00 42 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/adl/variants/hz/Makefile.mk b/src/mainboard/starlabs/adl/variants/hz/Makefile.mk new file mode 100644 index 0000000000..bfea7ef255 --- /dev/null +++ b/src/mainboard/starlabs/adl/variants/hz/Makefile.mk @@ -0,0 +1,12 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += romstage.c + +ramstage-y += devtree.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c +ramstage-y += ramstage.c + +$(call add_vbt_to_cbfs, vbt_native_res.bin, data_native_res.vbt) diff --git a/src/mainboard/starlabs/adl/variants/hz/board.fmd b/src/mainboard/starlabs/adl/variants/hz/board.fmd new file mode 100644 index 0000000000..2197262237 --- /dev/null +++ b/src/mainboard/starlabs/adl/variants/hz/board.fmd @@ -0,0 +1,14 @@ +FLASH 0x1000000 { + SI_ALL 0x600000 { + SI_DESC 0x1000 + SI_ME 0x411000 + } + SI_BIOS 0xa00000 { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + SMMSTORE@0x30000 0x80000 + CONSOLE@0xB0000 0x20000 + FMAP@0xD0000 0x1000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/adl/variants/hz/data.vbt b/src/mainboard/starlabs/adl/variants/hz/data.vbt new file mode 100644 index 0000000000..a2adefc8b2 Binary files /dev/null and b/src/mainboard/starlabs/adl/variants/hz/data.vbt differ diff --git a/src/mainboard/starlabs/adl/variants/hz/data_native_res.vbt b/src/mainboard/starlabs/adl/variants/hz/data_native_res.vbt new file mode 100644 index 0000000000..7e4f64ad7f Binary files /dev/null and b/src/mainboard/starlabs/adl/variants/hz/data_native_res.vbt differ diff --git a/src/mainboard/starlabs/adl/variants/hz/devicetree.cb b/src/mainboard/starlabs/adl/variants/hz/devicetree.cb new file mode 100644 index 0000000000..229ce37de4 --- /dev/null +++ b/src/mainboard/starlabs/adl/variants/hz/devicetree.cb @@ -0,0 +1,240 @@ +chip soc/intel/alderlake + # FSP UPDs + register "eist_enable" = "true" + register "enable_c6dram" = "true" + register "energy_efficient_turbo" = "true" + register "sagv" = "SaGv_Enabled" + + # Serial I/O + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoSkipInit, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + }" + + register "common_soc_config" = "{ + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + }" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + }" + + # Power + register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_1_MS" + register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_3S" + register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S" + register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS" + + device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "6" + # [DDIA] eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # [DDIB] HDMI + register "device[1].name" = ""DD01"" + # [TCP0] Type-C + register "device[2].name" = ""DD02"" + # [TCP1] Type-C + register "device[3].name" = ""DD03"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))" + # [TCP2] N/A + register "device[4].name" = ""DD04"" + # [TCP3] N/A + register "device[5].name" = ""DD05"" + device generic 0 on end + end + + register "ddi_portA_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + end + device ref gna on end + device ref xhci on + # Left Rear USB 2.0 Type-C 3289 mil + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" + + # Left Front USB 3.0 Type C + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # Right USB 3.0 Hub + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # Webcam 3249 mil + register "usb2_ports[CONFIG_CCD_PORT]" = "USB2_PORT_SHORT(OC_SKIP)" + + # Internal Bluetooth 1874 mil + register "usb2_ports[9]" = "USB2_PORT_SHORT(OC_SKIP)" + + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""Left Back USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_ONLY" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device ref usb2_port1 on end + end + + chip drivers/usb/acpi + register "desc" = ""Left Front USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Front USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))" + device ref usb3_port4 on end + end + + chip drivers/usb/acpi + register "desc" = ""Right USB 3.0 Hub"" + register "type" = "UPC_TYPE_HUB" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(0, 2))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""Right USB 3.0 Hub"" + register "type" = "UPC_TYPE_HUB" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(0, 2))" + device ref usb3_port1 on end + end + + chip drivers/usb/acpi + register "desc" = ""Internal Webcam"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device ref usb2_port5 on end + end + + chip drivers/usb/acpi + register "desc" = ""CNVi Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "is_intel_bluetooth" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_VGPIO_0)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + register "group" = "ACPI_PLD_GROUP(0, 4)" + device ref usb2_port10 on end + end + end + end + end + device ref i2c0 on end + device ref i2c3 on + chip drivers/i2c/hid + register "generic.hid" = ""STAR0001"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E12_IRQ)" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device ref shared_sram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "add_acpi_dma_property" = "true" + register "cnvi_enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end + device ref pcie_rp9 on # SSD x4 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_detect_timeout_ms = 50, + + }" + smbios_slot_desc "SlotTypeM2Socket3" + "SlotLengthLong" + "M.2/M 2280" + "SlotDataBusWidth4X" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" + register "srcclk_pin" = "0" + register "is_storage" = "true" + register "add_acpi_dma_property" = "true" + register "skip_on_off_support" = "true" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "true" + device generic 0 on end + end + end + device ref uart0 on end + device ref pch_espi on + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x00fc0201" + register "gen3_dec" = "0x000c0081" + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + + chip ec/starlabs/merlin + # Port pair 4Eh/4Fh + device pnp 4e.01 off end # Com 1 + device pnp 4e.02 off end # Com 2 + device pnp 4e.04 off end # System Wake-Up + device pnp 4e.05 off end # PS/2 Mouse + device pnp 4e.06 on # PS/2 Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + end + device pnp 4e.0a off end # Consumer IR + device pnp 4e.0f off end # Shared Memory/Flash Interface + device pnp 4e.10 off end # RTC-like Timer + device pnp 4e.11 off end # Power Management Channel 1 + device pnp 4e.12 off end # Power Management Channel 2 + device pnp 4e.13 off end # Serial Peripheral Interface + device pnp 4e.14 off end # Platform EC Interface + device pnp 4e.17 off end # Power Management Channel 3 + device pnp 4e.18 off end # Power Management Channel 4 + device pnp 4e.19 off end # Power Management Channel 5 + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use usb3_port4 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port7 as usb2_port + use usb3_port1 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref hda on + subsystemid 0x1e50 0x7038 + register "pch_hda_sdi_enable[0]" = "true" + register "pch_hda_dsp_enable" = "true" + register "pch_hda_audio_link_hda_enable" = "true" + register "pch_hda_idisp_codec_enable" = "true" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + end + device ref smbus on end + end +end diff --git a/src/mainboard/starlabs/adl/variants/hz/devtree.c b/src/mainboard/starlabs/adl/variants/hz/devtree.c new file mode 100644 index 0000000000..3ae2d08956 --- /dev/null +++ b/src/mainboard/starlabs/adl/variants/hz/devtree.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void devtree_update(void) +{ + config_t *cfg = config_of_soc(); + update_power_limits(cfg); + + /* Enable/Disable WiFi based on CMOS settings */ + if (get_uint_option("wifi", 1) == 0) + DEV_PTR(cnvi_wifi)->enabled = 0; + + /* Enable/Disable Bluetooth based on CMOS settings */ + if (get_uint_option("bluetooth", 1) == 0) + cfg->usb2_ports[9].enable = 0; + + /* Enable/Disable Webcam based on CMOS settings */ + if (get_uint_option("webcam", 1) == 0) + cfg->usb2_ports[CONFIG_CCD_PORT].enable = 0; + + /* Enable/Disable GNA based on CMOS settings */ + if (get_uint_option("gna", 0) == 0) + DEV_PTR(gna)->enabled = 0; +} diff --git a/src/mainboard/starlabs/adl/variants/hz/gpio.c b/src/mainboard/starlabs/adl/variants/hz/gpio.c new file mode 100644 index 0000000000..a72cc6e157 --- /dev/null +++ b/src/mainboard/starlabs/adl/variants/hz/gpio.c @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* Early pad configuration in bootblock */ +const struct pad_config early_gpio_table[] = { + /* Debug Connector */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* RXD */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* TXD */ +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage. */ +const struct pad_config gpio_table[] = { + /* General Purpose I/O Deep */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* Battery Low */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* Charger Connected */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* Power Button */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* Sleep S3 */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* Sleep S4 */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* Bluetooth Suspend */ + + /* eSPI - Configure automatically on reset */ + // PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1), /* eSPI IO 0 */ + // PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1), /* eSPI IO 1 */ + // PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1), /* eSPI IO 2 */ + // PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A3, UP_20K, DEEP, NF1), /* eSPI IO 3 */ + // PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A4, UP_20K, DEEP, NF1), /* eSPI CS 0 */ + // PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A9, UP_20K, DEEP, NF1), /* eSPI Clk */ + // PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1), /* eSPI Reset */ + + /* Touchpad */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* Data */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), /* Clock */ + PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST), /* Interrupt */ + + /* SSD */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* Clock Request 0 */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), /* Reset */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), /* Enable */ + + /* Wireless */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* BRI Data */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), /* BRI Response */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* RGI Data */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), /* RGI Response */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* RF Reset */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), /* Modem Clock Request */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), /* WiFi RF Kill */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), /* Bluetooth RF Kill */ + + /* Display */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* eDP Hot Plug */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* HDMI Hot Plug */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* HDMI Clock */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* HDMI Data */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* TCP1 Hot Plug */ + + /* High-Definition Audio */ + PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1), /* Clock */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), /* Sync */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), /* Data Output */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* Data Input */ + PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1), /* Reset */ + + /* PCH */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10 Gate */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* Platform Reset */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* Vendor ID 0 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* Vendor ID 1 */ + PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT), /* Processor Hot */ + + /* TPM */ + PAD_CFG_GPI_APIC_LOW(GPP_E2, NONE, PLTRST), /* Interrupt */ + + /* SMBus */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* Clock */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* Data */ + PAD_CFG_GPO(GPP_E8, 1, DEEP), /* DRAM Sleep */ + + /* Config Straps [ Low / High ] */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* Top Swap [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* Reboot Support [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* TLS Confidentiality [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_C5, 0, PLTRST), /* eSPI [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_E6, 0, PLTRST), /* JTAG ODT [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_H1, 0, PLTRST), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_E19, 0, PLTRST), /* TBT LSX #0 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_E21, 0, PLTRST), /* TBT LSX #1 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_D10, 0, PLTRST), /* TBT LSX #2 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_D12, 0, PLTRST), /* TBT LSX #3 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_F7, 0, PLTRST), /* MCRO LDO [ Disabled / Bypass ] */ + PAD_CFG_GPO(GPD7, 0, PLTRST), /* RTC Clock Delay [ Disabled / 95ms ] */ + + PAD_NC(GPD2, NONE), + PAD_NC(GPD6, NONE), + PAD_NC(GPD9, NONE), + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), + + PAD_NC(GPP_A5, NONE), + PAD_NC(GPP_A6, NONE), + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A14, NONE), + PAD_NC(GPP_A15, NONE), + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_NC(GPP_B11, NONE), + PAD_NC(GPP_B12, NONE), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_NC(GPP_B23, NONE), + PAD_NC(GPP_B24, NONE), + PAD_NC(GPP_B25, NONE), + + PAD_NC(GPP_C3, NONE), + PAD_NC(GPP_C4, NONE), + PAD_NC(GPP_C6, NONE), + PAD_NC(GPP_C7, NONE), + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E7, NONE), + PAD_NC(GPP_E9, NONE), + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E13, NONE), + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_NC(GPP_E17, NONE), + PAD_NC(GPP_E18, NONE), + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + PAD_NC(GPP_F6, NONE), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + PAD_NC(GPP_H2, NONE), + PAD_NC(GPP_H3, NONE), + PAD_NC(GPP_H4, NONE), + PAD_NC(GPP_H5, NONE), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + PAD_NC(GPP_T0, NONE), + PAD_NC(GPP_T1, NONE), + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), + PAD_NC(GPP_T4, NONE), + PAD_NC(GPP_T5, NONE), + PAD_NC(GPP_T6, NONE), + PAD_NC(GPP_T7, NONE), + PAD_NC(GPP_T8, NONE), + PAD_NC(GPP_T9, NONE), + PAD_NC(GPP_T10, NONE), + PAD_NC(GPP_T11, NONE), + PAD_NC(GPP_T12, NONE), + PAD_NC(GPP_T13, NONE), + PAD_NC(GPP_T14, NONE), + PAD_NC(GPP_T15, NONE), + + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/starlabs/adl/variants/hz/hda_verb.c b/src/mainboard/starlabs/adl/variants/hz/hda_verb.c new file mode 100644 index 0000000000..813c0f0458 --- /dev/null +++ b/src/mainboard/starlabs/adl/variants/hz/hda_verb.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ + 0x1e507038, /* Subsystem ID */ + 18, /* Number of verb entries */ + + /* Reset Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID */ + AZALIA_SUBVENDOR(0, 0x1e507038), + + /* Pin Widget Verb-table */ + AZALIA_PIN_CFG(0, ALC269_DMIC12, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_MOBILE_LID_INSIDE, + AZALIA_MIC_IN, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, + 0 + )), + AZALIA_PIN_CFG(0, ALC269_SPEAKERS, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL | AZALIA_FRONT, + AZALIA_SPEAKER, + AZALIA_OTHER_ANALOG, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, + 0 + )), + AZALIA_PIN_CFG(0, ALC269_VC_HP_OUT, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 2, + 0 + )), + AZALIA_PIN_CFG(0, ALC269_MIC1, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 4, + 0 + )), + AZALIA_PIN_CFG(0, ALC269_MONO, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_MIC2, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_LINE1, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_LINE2, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_PC_BEEP, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_SPDIF_OUT, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, ALC269_VB_HP_OUT, AZALIA_PIN_CFG_NC(0)), + + /* ALC269 Default 1 */ + 0x02050018, + 0x02040184, + 0x0205001c, + 0x02044800, + /* ALC269 Default 2 */ + 0x02050024, + 0x02040000, + 0x02050004, + 0x02040080, + /* ALC269 Default 3 */ + 0x02050008, + 0x02040000, + 0x0205000c, + 0x02043f00, + /* ALC269 Default 4 */ + 0x02050015, + 0x02048002, + 0x02050015, + 0x02048002, + /* Widget 0x0c */ + 0x00c37080, + 0x00270610, + 0x00d37080, + 0x00370610, +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/starlabs/adl/variants/hz/ramstage.c b/src/mainboard/starlabs/adl/variants/hz/ramstage.c new file mode 100644 index 0000000000..370f5c8769 --- /dev/null +++ b/src/mainboard/starlabs/adl/variants/hz/ramstage.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *supd) +{ + configure_pin_mux(supd); +} + +const char *mainboard_vbt_filename(void) +{ + if (get_uint_option("display_native_res", 0) == 1) + return "vbt_native_res.bin"; + + return "vbt.bin"; +} diff --git a/src/mainboard/starlabs/adl/variants/hz/romstage.c b/src/mainboard/starlabs/adl/variants/hz/romstage.c new file mode 100644 index 0000000000..9162509387 --- /dev/null +++ b/src/mainboard/starlabs/adl/variants/hz/romstage.c @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg mem_config = { + .type = MEM_TYPE_LP5X, + + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 10, 14, 13, 12, 9, 11, 15, 8 }, + .dq1 = { 4, 1, 7, 3, 5, 0, 2, 6 }, + }, + .ddr1 = { + .dq0 = { 2, 7, 6, 0, 1, 3, 5, 4 }, + .dq1 = { 13, 11, 9, 8, 10, 14, 12, 15 }, + }, + .ddr2 = { + .dq0 = { 7, 0, 1, 6, 4, 5, 2, 3 }, + .dq1 = { 8, 10, 9, 11, 15, 13, 12, 14 }, + }, + .ddr3 = { + .dq0 = { 2, 0, 3, 1, 4, 5, 7, 6 }, + .dq1 = { 10, 9, 14, 11, 12, 13, 15, 8 }, + }, + .ddr4 = { + .dq0 = { 3, 2, 1, 0, 7, 4, 6, 5 }, + .dq1 = { 8, 10, 11, 9, 14, 13, 12, 15 }, + }, + .ddr5 = { + .dq0 = { 8, 9, 10, 11, 12, 13, 14, 15 }, + .dq1 = { 7, 6, 5, 4, 3, 2, 1, 0 }, + }, + .ddr6 = { + .dq0 = { 13, 12, 15, 14, 9, 8, 11, 10 }, + .dq1 = { 5, 4, 7, 6, 3, 1, 2, 0 }, + }, + .ddr7 = { + .dq0 = { 3, 1, 2, 0, 4, 6, 5, 7 }, + .dq1 = { 15, 12, 9, 8, 11, 10, 13, 14 }, + }, + }, + .lpx_dqs_map = { + .ddr0 = { + .dqs0 = 1, + .dqs1 = 0, + }, + .ddr1 = { + .dqs0 = 0, + .dqs1 = 1, + }, + .ddr2 = { + .dqs0 = 0, + .dqs1 = 1, + }, + .ddr3 = { + .dqs0 = 0, + .dqs1 = 1, + }, + .ddr4 = { + .dqs0 = 1, + .dqs1 = 0, + }, + .ddr5 = { + .dqs0 = 0, + .dqs1 = 1, + }, + .ddr6 = { + .dqs0 = 0, + .dqs1 = 1, + }, + .ddr7 = { + .dqs0 = 1, + .dqs1 = 0, + } + }, + + .ect = true, + .UserBd = BOARD_TYPE_ULT_ULX, + .LpDdrDqDqsReTraining = true, + + .lp5x_config = { + .ccc_config = 0x00, + } + }; + + const bool half_populated = true; + + const struct mem_spd lpddr5_spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, + .cbfs_index = get_uint_option("memory_speed", 1), + }; + + memcfg_init(mupd, &mem_config, &lpddr5_spd_info, half_populated); + + const uint8_t vtd = get_uint_option("vtd", 1); + mupd->FspmConfig.VtdDisable = !vtd; +}; diff --git a/src/mainboard/starlabs/adl/vboot.c b/src/mainboard/starlabs/adl/vboot.c new file mode 100644 index 0000000000..8511825004 --- /dev/null +++ b/src/mainboard/starlabs/adl/vboot.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +int get_recovery_mode_switch(void) +{ + return 0; +}