From dcd50d45dc01fbbb4668910a9da72136ef365a48 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Mon, 20 Jan 2025 11:39:22 +0000 Subject: [PATCH] mb/starlabs/starlite_adl: Enable TLS Confidentiality GPIO This board does not have a 20K Pull Down resistor fitted here, meaning this will not change anything. However, it unifies the the configuration with the other Star Labs boards. Change-Id: Iee0adea21c124e0a421a1506310944cc883a73fb Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/86066 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c index dac68965e8..002d0e5a8f 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c @@ -148,7 +148,7 @@ const struct pad_config gpio_table[] = { /* C2: TLS Confidentiality Weak Internal PD 20K Low: Disabled High: Enabled */ - PAD_CFG_GPO(GPP_C2, 0, DEEP), + PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* C3: SML 0 Clock */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* C4: SML 0 Data */