From dcbe591201ad92ab3a7c2e3173a4dc19b4247528 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Tue, 1 Jul 2025 08:38:32 +0200 Subject: [PATCH] mb/siemens/mc_rpl: Use SPD data from HWInfo instead of from CBFS Siemens boards store their memory configuration data (SPD) in a field inside the HWInfo block (which itself is located in CBFS). This patch removes all *spd.hex-files and uses HWInfo instead for the SPD data source. In addition, the memory data swizzling is updated to reflect the board wiring so that DRAM can work properly. Change-Id: I63d6e7c4543b7d99a4b1815c8ee81efcb6a87b94 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/88259 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer --- src/mainboard/siemens/mc_rpl/Kconfig | 6 +- src/mainboard/siemens/mc_rpl/Makefile.mk | 5 - src/mainboard/siemens/mc_rpl/memory.c | 349 +----------------- src/mainboard/siemens/mc_rpl/memory_rpl.c | 28 -- .../siemens/mc_rpl/romstage_fsp_params.c | 84 +---- src/mainboard/siemens/mc_rpl/spd/Makefile.mk | 10 - .../siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex | 32 -- .../siemens/mc_rpl/spd/adlrvp_lp4.spd.hex | 32 -- .../siemens/mc_rpl/spd/adlrvp_lp5.spd.hex | 32 -- .../siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex | 32 -- .../siemens/mc_rpl/spd/empty.spd.hex | 32 -- 11 files changed, 42 insertions(+), 600 deletions(-) delete mode 100644 src/mainboard/siemens/mc_rpl/memory_rpl.c delete mode 100644 src/mainboard/siemens/mc_rpl/spd/Makefile.mk delete mode 100644 src/mainboard/siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex delete mode 100644 src/mainboard/siemens/mc_rpl/spd/adlrvp_lp4.spd.hex delete mode 100644 src/mainboard/siemens/mc_rpl/spd/adlrvp_lp5.spd.hex delete mode 100644 src/mainboard/siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex delete mode 100644 src/mainboard/siemens/mc_rpl/spd/empty.spd.hex diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig index 4c04775b09..c08139e619 100644 --- a/src/mainboard/siemens/mc_rpl/Kconfig +++ b/src/mainboard/siemens/mc_rpl/Kconfig @@ -15,10 +15,10 @@ config BOARD_SIEMENS_BASEBOARD_MC_RPL select DRIVERS_USB_ACPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select HAVE_SPD_IN_CBFS select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SOC_INTEL_CSE_LITE_SKU + select USE_SIEMENS_HWILIB config BOARD_SIEMENS_MC_RPL1 @@ -60,6 +60,10 @@ config UART_FOR_CONSOLE int default 0 +config DIMM_SPD_SIZE + int + default 256 + config DRIVER_TPM_SPI_BUS default 0x2 if BOARD_SIEMENS_MC_RPL1 diff --git a/src/mainboard/siemens/mc_rpl/Makefile.mk b/src/mainboard/siemens/mc_rpl/Makefile.mk index e6c0dd62d1..872ab9e94d 100644 --- a/src/mainboard/siemens/mc_rpl/Makefile.mk +++ b/src/mainboard/siemens/mc_rpl/Makefile.mk @@ -1,15 +1,10 @@ ## SPDX-License-Identifier: GPL-2.0-only -subdirs-y += spd - bootblock-y += bootblock.c romstage-y += romstage_fsp_params.c romstage-y += board_id.c romstage-y += memory.c -ifeq ($(CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC),y) -romstage-y += memory_rpl.c -endif ramstage-y += mainboard.c ramstage-y += board_id.c diff --git a/src/mainboard/siemens/mc_rpl/memory.c b/src/mainboard/siemens/mc_rpl/memory.c index 160059921b..40b4c971d2 100644 --- a/src/mainboard/siemens/mc_rpl/memory.c +++ b/src/mainboard/siemens/mc_rpl/memory.c @@ -4,124 +4,42 @@ #include #include -#include "board_id.h" - -static const struct mb_cfg ddr4_mem_config = { - .type = MEM_TYPE_DDR4, - - .rcomp = { - /* Baseboard uses only 100ohm Rcomp resistor */ - .resistor = 100, - - /* Baseboard Rcomp target values */ - .targets = { 50, 20, 25, 25, 25 }, - }, - - .ect = true, /* Early Command Training */ - - .UserBd = BOARD_TYPE_MOBILE, - - .LpDdrDqDqsReTraining = 1, - - .ddr_config = { - .dq_pins_interleaved = false, - }, -}; - -static const struct mb_cfg lpddr4_mem_config = { - .type = MEM_TYPE_LP4X, - - /* DQ byte map */ - .lpx_dq_map = { - .ddr0 = { - .dq0 = { 0, 2, 3, 1, 6, 7, 5, 4, }, - .dq1 = { 10, 8, 11, 9, 14, 12, 13, 15, }, - }, - .ddr1 = { - .dq0 = { 12, 8, 14, 10, 11, 13, 15, 9, }, - .dq1 = { 5, 0, 7, 3, 6, 2, 1, 4, }, - }, - .ddr2 = { - .dq0 = { 3, 0, 2, 1, 6, 5, 4, 7, }, - .dq1 = { 12, 13, 14, 15, 10, 9, 8, 11, }, - }, - .ddr3 = { - .dq0 = { 2, 6, 7, 1, 3, 4, 0, 5, }, - .dq1 = { 9, 13, 8, 15, 14, 11, 12, 10, }, - }, - .ddr4 = { - .dq0 = { 3, 0, 1, 2, 7, 4, 6, 5, }, - .dq1 = { 10, 8, 11, 9, 14, 13, 12, 15, }, - }, - .ddr5 = { - .dq0 = { 10, 12, 14, 8, 9, 13, 15, 11, }, - .dq1 = { 3, 7, 6, 2, 0, 4, 5, 1, }, - }, - .ddr6 = { - .dq0 = { 12, 15, 14, 13, 9, 10, 11, 8, }, - .dq1 = { 7, 4, 6, 5, 0, 1, 3, 2, }, - }, - .ddr7 = { - .dq0 = { 0, 2, 4, 3, 1, 6, 7, 5, }, - .dq1 = { 13, 9, 10, 11, 8, 12, 14, 15, }, - }, - }, - - /* DQS CPU<>DRAM map */ - .lpx_dqs_map = { - .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, - }, - - .LpDdrDqDqsReTraining = 1, - - .ect = true, /* Early Command Training */ - - .UserBd = BOARD_TYPE_MOBILE, -}; - -static const struct mb_cfg lp5_mem_config = { +static const struct mb_cfg mc_rpl1_lp5_mem_config = { .type = MEM_TYPE_LP5X, /* DQ byte map */ .lpx_dq_map = { .ddr0 = { - .dq0 = { 3, 2, 1, 0, 5, 4, 6, 7, }, - .dq1 = { 15, 14, 12, 13, 8, 9, 10, 11, }, + .dq0 = { 0, 3, 2, 1, 4, 5, 7, 6, }, + .dq1 = { 14, 12, 13, 15, 8, 10, 9, 11, }, }, .ddr1 = { - .dq0 = { 0, 2, 3, 1, 5, 7, 4, 6, }, - .dq1 = { 14, 13, 15, 12, 8, 9, 11, 10, }, + .dq0 = { 1, 0, 2, 3, 6, 4, 7, 5, }, + .dq1 = { 15, 13, 12, 14, 8, 11, 10, 9, }, }, .ddr2 = { - .dq0 = { 1, 2, 0, 3, 4, 6, 5, 7, }, - .dq1 = { 15, 13, 12, 14, 9, 10, 8, 11, }, + .dq0 = { 2, 1, 3, 0, 7, 6, 4, 5, }, + .dq1 = { 14, 12, 13, 15, 9, 10, 11, 8, }, }, .ddr3 = { - .dq0 = { 2, 1, 3, 0, 7, 4, 5, 6, }, - .dq1 = { 13, 12, 15, 14, 9, 11, 8, 10, }, + .dq0 = { 1, 2, 3, 0, 6, 4, 7, 5, }, + .dq1 = { 13, 15, 12, 14, 8, 11, 10, 9, }, }, .ddr4 = { - .dq0 = { 1, 2, 3, 0, 6, 4, 5, 7, }, - .dq1 = { 15, 13, 14, 12, 10, 9, 8, 11, }, + .dq0 = { 2, 3, 0, 1, 5, 7, 4, 6, }, + .dq1 = { 14, 12, 13, 15, 10, 9, 11, 8, }, }, .ddr5 = { - .dq0 = { 1, 0, 3, 2, 6, 7, 4, 5, }, - .dq1 = { 14, 12, 15, 13, 8, 9, 10, 11, }, + .dq0 = { 1, 2, 3, 0, 6, 4, 7, 5, }, + .dq1 = { 15, 13, 12, 14, 11, 9, 10, 8, }, }, .ddr6 = { - .dq0 = { 0, 2, 1, 3, 4, 7, 5, 6, }, - .dq1 = { 12, 13, 15, 14, 9, 11, 10, 8, }, + .dq0 = { 3, 1, 2, 0, 5, 4, 7, 6, }, + .dq1 = { 15, 13, 14, 12, 9, 10, 8, 11, }, }, .ddr7 = { - .dq0 = { 3, 2, 1, 0, 5, 4, 6, 7, }, - .dq1 = { 13, 15, 11, 12, 10, 9, 14, 8, }, + .dq0 = { 2, 3, 1, 0, 5, 4, 7, 6, }, + .dq1 = { 14, 15, 10, 11, 13, 8, 9, 12, }, }, }, @@ -137,215 +55,9 @@ static const struct mb_cfg lp5_mem_config = { .ddr7 = { .dqs0 = 0, .dqs1 = 1 } }, - .ect = true, /* Early Command Training */ - - .LpDdrDqDqsReTraining = 1, - - .UserBd = BOARD_TYPE_MOBILE, - - .lp5x_config = { - .ccc_config = 0xff, - }, -}; - -static const struct mb_cfg ddr5_mem_config = { - .type = MEM_TYPE_DDR5, - - .rcomp = { - /* Baseboard uses only 100ohm Rcomp resistor */ - .resistor = 100, - - /* Baseboard Rcomp target values */ - .targets = { 50, 30, 30, 30, 27 }, - }, - - .ect = true, /* Early Command Training */ - - .UserBd = BOARD_TYPE_MOBILE, - - .LpDdrDqDqsReTraining = 1, - - .ddr_config = { - .dq_pins_interleaved = false, - } -}; - -static const struct mb_cfg adlm_lp4_mem_config = { - .type = MEM_TYPE_LP4X, - - /* DQ byte map */ - .lpx_dq_map = { - .ddr0 = { - .dq0 = { 13, 12, 14, 8, 11, 10, 9, 15, }, /* DDR0_DQ0[7:0] */ - .dq1 = { 3, 2, 7, 6, 0, 1, 5, 4, }, /* DDR0_DQ1[7:0] */ - }, - .ddr1 = { - .dq0 = { 11, 15, 10, 9, 12, 8, 14, 13, }, /* DDR1_DQ0[7:0] */ - .dq1 = { 0, 1, 7, 6, 2, 5, 4, 3, }, /* DDR1_DQ1[7:0] */ - }, - .ddr2 = { - .dq0 = { 6, 7, 3, 2, 0, 4, 1, 5, }, /* DDR2_DQ0[7:0] */ - .dq1 = { 14, 8, 13, 12, 11, 9, 10, 15, }, /* DDR2_DQ1[7:0] */ - }, - .ddr3 = { - .dq0 = { 2, 6, 7, 3, 1, 5, 0, 4, }, /* DDR3_DQ0[7:0] */ - .dq1 = { 8, 14, 13, 12, 10, 11, 9, 15, }, /* DDR3_DQ1[7:0] */ - }, - .ddr4 = { - .dq0 = { 8, 14, 13, 12, 10, 11, 9, 15, }, /* DDR3_DQ1[7:0] */ - .dq1 = { 1, 0, 5, 4, 6, 2, 3, 7, }, /* DDR4_DQ1[7:0] */ - }, - .ddr5 = { - .dq0 = { 8, 10, 9, 12, 14, 11, 13, 15, }, /* DDR5_DQ0[7:0] */ - .dq1 = { 0, 7, 2, 6, 3, 1, 4, 5, }, /* DDR5_DQ1[7:0] */ - }, - .ddr6 = { - .dq0 = { 14, 12, 9, 8, 15, 10, 13, 11, }, /* DDR6_DQ0[7:0] */ - .dq1 = { 4, 0, 5, 6, 3, 2, 1, 7, }, /* DDR6_DQ1[7:0] */ - }, - .ddr7 = { - .dq0 = { 10, 15, 12, 11, 9, 14, 13, 8, }, /* DDR7_DQ0[7:0] */ - .dq1 = { 7, 1, 2, 3, 6, 0, 5, 4, }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .lpx_dqs_map = { - .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr7 = { .dqs0 = 1, .dqs1 = 0 } - }, - - .ect = true, /* Early Command Training */ - - .CmdMirror = 0xCC, - - .LpDdrDqDqsReTraining = 1, - - .UserBd = BOARD_TYPE_ULT_ULX_T4, -}; - -static const struct mb_cfg adlm_lp5_mem_config = { - .type = MEM_TYPE_LP5X, - - /* DQ byte map */ - .lpx_dq_map = { - .ddr0 = { - .dq0 = { 4, 5, 7, 6, 3, 2, 1, 0, }, - .dq1 = { 12, 10, 8, 15, 11, 9, 14, 13, }, - }, - .ddr1 = { - .dq0 = { 1, 0, 2, 3, 7, 4, 5, 6, }, - .dq1 = { 14, 15, 10, 11, 13, 12, 8, 9, }, - }, - .ddr2 = { - .dq0 = { 7, 4, 2, 0, 3, 1, 6, 5, }, - .dq1 = { 14, 13, 15, 12, 8, 9, 10, 11, }, - }, - .ddr3 = { - .dq0 = { 3, 2, 0, 1, 7, 5, 6, 4, }, - .dq1 = { 12, 14, 15, 13, 11, 8, 10, 9, }, - }, - .ddr4 = { - .dq0 = { 2, 3, 0, 1, 6, 4, 7, 5, }, - .dq1 = { 14, 9, 11, 13, 12, 8, 15, 10, }, - }, - .ddr5 = { - .dq0 = { 4, 7, 3, 1, 5, 2, 6, 0, }, - .dq1 = { 14, 8, 11, 9, 12, 15, 10, 13, }, - }, - .ddr6 = { - .dq0 = { 10, 11, 13, 9, 15, 12, 8, 14, }, - .dq1 = { 2, 4, 7, 0, 6, 3, 5, 1, }, - }, - .ddr7 = { - .dq0 = { 13, 15, 11, 14, 10, 12, 8, 9, }, - .dq1 = { 6, 5, 4, 7, 3, 1, 2, 0, }, - }, - }, - - /* DQS CPU<>DRAM map */ - .lpx_dqs_map = { - .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr7 = { .dqs0 = 1, .dqs1 = 0 } - }, - .ect = false, /* Early Command Training */ - .UserBd = BOARD_TYPE_ULT_ULX_T4, - - .lp5x_config = { - .ccc_config = 0xff, - }, -}; - -static const struct mb_cfg adln_lp5_mem_config = { - .type = MEM_TYPE_LP5X, - - /* DQ byte map */ - .lpx_dq_map = { - .ddr0 = { - .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, - .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, - }, - .ddr1 = { - .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, - .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, - }, - .ddr2 = { - .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, - .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, - }, - .ddr3 = { - .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, - .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, - }, - .ddr4 = { - .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, - .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, - }, - .ddr5 = { - .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, - .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, - }, - .ddr6 = { - .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, - .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, - }, - .ddr7 = { - .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, - .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, - }, - }, - - /* DQS CPU<>DRAM map */ - .lpx_dqs_map = { - .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr7 = { .dqs0 = 0, .dqs1 = 1 } - }, - - .ect = true, /* Early Command Training */ - - .UserBd = BOARD_TYPE_ULT_ULX, - - .LpDdrDqDqsReTraining = 1, + .UserBd = BOARD_TYPE_MOBILE, .lp5x_config = { .ccc_config = 0xff, @@ -354,28 +66,5 @@ static const struct mb_cfg adln_lp5_mem_config = { const struct mb_cfg *variant_memory_params(void) { - int board_id = get_board_id(); - - switch (board_id) { - case ADL_P_LP4_1: - case ADL_P_LP4_2: - return &lpddr4_mem_config; - case ADL_P_DDR4_1: - case ADL_P_DDR4_2: - return &ddr4_mem_config; - case ADL_P_DDR5_1: - case ADL_P_DDR5_2: - return &ddr5_mem_config; - case ADL_P_LP5_1: - case ADL_P_LP5_2: - return &lp5_mem_config; - case ADL_M_LP4: - return &adlm_lp4_mem_config; - case ADL_M_LP5: - return &adlm_lp5_mem_config; - case ADL_N_LP5: - return &adln_lp5_mem_config; - default: - die("unsupported board id : 0x%x\n", board_id); - } + return &mc_rpl1_lp5_mem_config; } diff --git a/src/mainboard/siemens/mc_rpl/memory_rpl.c b/src/mainboard/siemens/mc_rpl/memory_rpl.c deleted file mode 100644 index 8302a06d1f..0000000000 --- a/src/mainboard/siemens/mc_rpl/memory_rpl.c +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -#include "board_id.h" - -void rpl_memory_params(FSPM_UPD *memupd) -{ - FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; - - int board_id = get_board_id(); - - switch (board_id) { - case ADL_P_LP4_1: - case ADL_P_LP4_2: - case ADL_P_DDR4_1: - case ADL_P_DDR4_2: - case ADL_P_DDR5_1: - case ADL_P_DDR5_2: - default: - return; - case ADL_P_LP5_1: - case ADL_P_LP5_2: - mem_cfg->Lp5BankMode = 1; - return; - } -} diff --git a/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c b/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c index 46640b6aad..962b514d2f 100644 --- a/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c +++ b/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c @@ -2,26 +2,11 @@ #include #include +#include #include #include #include #include -#include "board_id.h" - -#define SPD_ID_MASK 0x7 - -static size_t get_spd_index(void) -{ - uint8_t board_id = get_board_id(); - size_t spd_index; - - printk(BIOS_INFO, "board id is 0x%x\n", board_id); - - spd_index = board_id & SPD_ID_MASK; - - printk(BIOS_INFO, "SPD index is 0x%x\n", (unsigned int)spd_index); - return spd_index; -} /* * ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's @@ -49,7 +34,22 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; const struct mb_cfg *mem_config = variant_memory_params(); - int board_id = get_board_id(); + + static struct mem_spd spd_info; + static uint8_t spd_data[CONFIG_DIMM_SPD_SIZE]; + const char *cbfs_hwi_name = "hwinfo.hex"; + + /* Initialize SPD information for LPDDR5 from HW-Info. */ + memset(spd_data, 0, sizeof(spd_data)); + if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) && + (hwilib_get_field(SPD, spd_data, 0x80) == 0x80)) { + spd_info.topo = MEM_TOPO_MEMORY_DOWN; + spd_info.spd_data.in_mem = true; + spd_info.spd_data.ptr = (uintptr_t)spd_data; + spd_info.spd_data.len = CONFIG_DIMM_SPD_SIZE; + } else { + die("No SPD in HW-Info found!\n"); + } /* * Set Raptor Lake specific new upds that Alder Lake doesn't have. @@ -57,55 +57,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) */ rpl_memory_params(memupd); - /* - * Alder Lake common meminit block driver considers bus width to be 128-bit and - * populates the meminit data accordingly. Alder Lake-N has single memory controller - * with 64-bit bus width. By setting half_populated to true, only the bottom half is - * populated. - * TODO: Implement __weak variant_is_half_populated(void) function. - */ - const bool half_populated = (CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) - || CONFIG(BOARD_INTEL_ADLRVP_N)); - - const struct mem_spd memory_down_spd_info = { - .topo = MEM_TOPO_MEMORY_DOWN, - .cbfs_index = get_spd_index(), - }; - - const struct mem_spd dimm_module_spd_info = { - .topo = MEM_TOPO_DIMM_MODULE, - .smbus = { - [0] = { - .addr_dimm[0] = 0x50, - .addr_dimm[1] = 0x51, - }, - [1] = { - .addr_dimm[0] = 0x52, - .addr_dimm[1] = 0x53, - }, - }, - }; - - switch (board_id) { - case ADL_P_DDR4_1: - case ADL_P_DDR4_2: - case ADL_P_DDR5_1: - memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated); - break; - case ADL_P_DDR5_2: - case ADL_P_LP4_1: - case ADL_P_LP4_2: - case ADL_P_LP5_1: - case ADL_P_LP5_2: - case ADL_M_LP4: - case ADL_M_LP5: - case ADL_N_LP5: - memcfg_init(memupd, mem_config, &memory_down_spd_info, half_populated); - break; - default: - die("Unknown board id = 0x%x\n", board_id); - break; - } + memcfg_init(memupd, mem_config, &spd_info, 0); if (CONFIG(GEN3_EXTERNAL_CLOCK_BUFFER)) configure_external_clksrc(m_cfg); diff --git a/src/mainboard/siemens/mc_rpl/spd/Makefile.mk b/src/mainboard/siemens/mc_rpl/spd/Makefile.mk deleted file mode 100644 index f503b6d959..0000000000 --- a/src/mainboard/siemens/mc_rpl/spd/Makefile.mk +++ /dev/null @@ -1,10 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -SPD_SOURCES = adlrvp_lp4 # 0b000 -SPD_SOURCES += empty # 0b001 -SPD_SOURCES += empty # 0b002 -SPD_SOURCES += adlrvp_lp5 # 0b003 -SPD_SOURCES += empty # 0b004 -SPD_SOURCES += empty # 0b005 -SPD_SOURCES += adlrvp_ddr5_mr # 0b006 -SPD_SOURCES += adlrvp_n_lp5 # 0b007 diff --git a/src/mainboard/siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex b/src/mainboard/siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex deleted file mode 100644 index 80ef521cfa..0000000000 --- a/src/mainboard/siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -30 08 12 03 04 00 20 62 00 00 00 00 60 00 00 00 -00 00 00 00 A1 01 E8 03 72 15 00 00 00 00 1E 41 -1E 41 1E 41 00 7D 1E BE 30 75 27 01 A0 00 82 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 47 AE -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -08 00 C2 C4 80 00 80 B3 80 11 00 00 00 00 00 00 -00 00 80 B3 80 11 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 0F 10 00 01 01 22 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 9C AD -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp4.spd.hex b/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp4.spd.hex deleted file mode 100644 index e1d338edbc..0000000000 --- a/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp4.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 -48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 -04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp5.spd.hex b/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp5.spd.hex deleted file mode 100644 index 2f2a31a33d..0000000000 --- a/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp5.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 10 13 0E 15 1A 95 08 00 40 00 00 02 01 00 00 -48 00 0A FF 92 55 05 00 AA 00 98 A8 90 90 06 C0 -03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 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00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex b/src/mainboard/siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex deleted file mode 100644 index 88a1f1f473..0000000000 --- a/src/mainboard/siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 10 13 0E 15 1A B5 08 00 40 00 00 0A 01 00 00 -48 00 0A FF 92 55 05 00 AA 00 90 A8 90 90 06 C0 -03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/siemens/mc_rpl/spd/empty.spd.hex b/src/mainboard/siemens/mc_rpl/spd/empty.spd.hex deleted file mode 100644 index 67b46cd239..0000000000 --- a/src/mainboard/siemens/mc_rpl/spd/empty.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 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