From dc9d6fdee3dc3d291838f09cf05596a9830700fe Mon Sep 17 00:00:00 2001 From: Pranava Y N Date: Fri, 28 Feb 2025 17:03:46 +0530 Subject: [PATCH] mb/google/brya/lisbon: Enable RTD3 for SSD Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. BUG=b:391612392 TEST=Run suspend_stress_test on lisbon and verify that the device suspends to S0ix. Change-Id: I124b63061650c85ed84324f3e1558a583a1875e0 Signed-off-by: Pranava Y N Reviewed-on: https://review.coreboot.org/c/coreboot/+/86645 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/mainboard/google/brya/variants/lisbon/overridetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/brya/variants/lisbon/overridetree.cb b/src/mainboard/google/brya/variants/lisbon/overridetree.cb index 4c3fffff6f..6c3eaf952a 100644 --- a/src/mainboard/google/brya/variants/lisbon/overridetree.cb +++ b/src/mainboard/google/brya/variants/lisbon/overridetree.cb @@ -149,6 +149,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end probe STORAGE STORAGE_NVME end #NVMe device ref tbt_pcie_rp0 off end