From dc68f5b265e4c6d96547f6e6da31763a91b6eddc Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Thu, 6 Nov 2025 11:28:09 -0800 Subject: [PATCH] soc/intel/pantherlake: Let common code set PL1 to TDP Update PL1 override values from a fixed value to zero, indicating that the platform should use the default TDP value. This change allows the common code to dynamically set PL1 according to the specific TDP SKU, improving flexibility and ensuring correct power limit configuration across different hardware variants. Previously, PL1 was hardcoded to 15 for some SKUs, which could lead to instabilities for SKUs with different TDP requirements. TEST=No instability was observed on certain Fatcat SKUs. Change-Id: Ibfb6b52aa15ad66740abc39f6f869dfa5e90de3c Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/89934 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Guvendik, Bora Reviewed-by: Ryu, Jamie M Reviewed-by: Kim, Wonkyu --- src/soc/intel/pantherlake/chipset_ptl.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb index e646c5dc4e..ccd727d6cd 100644 --- a/src/soc/intel/pantherlake/chipset_ptl.cb +++ b/src/soc/intel/pantherlake/chipset_ptl.cb @@ -3,7 +3,7 @@ chip soc/intel/pantherlake device cpu_cluster 0 on end register "power_limits_config[PTL_CORE_1]" = "{ - .tdp_pl1_override = 15, + .tdp_pl1_override = 0, /* Use TDP */ .tdp_pl2_override = 55, .tdp_pl4 = 163, .tdp_pl4_fastvmode = 150, @@ -24,7 +24,7 @@ chip soc/intel/pantherlake }" register "power_limits_config[PTL_CORE_2]" = "{ - .tdp_pl1_override = 15, + .tdp_pl1_override = 0, /* Use TDP */ .tdp_pl2_override = 55, .tdp_pl4 = 163, .tdp_pl4_fastvmode = 150, @@ -37,7 +37,7 @@ chip soc/intel/pantherlake }" register "power_limits_config[PTL_CORE_3]" = "{ - .tdp_pl1_override = 25, + .tdp_pl1_override = 0, /* Use TDP */ .tdp_pl2_override = 65, .tdp_pl4 = 175, .tdp_pl4_fastvmode = 160, @@ -58,7 +58,7 @@ chip soc/intel/pantherlake }" register "power_limits_config[PTL_CORE_4]" = "{ - .tdp_pl1_override = 25, + .tdp_pl1_override = 0, /* Use TDP */ .tdp_pl2_override = 65, .tdp_pl4 = 160, .tdp_pl4_fastvmode = 140