erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

This is the fix for MFGPT on those boards which have a cs5536 and ALSO

Browse source 
have a superio.
With this patch, alix1c and MFGPT work fine. Still need to test on Alix2c3, but it
is likely it will work.

Thanks to Marc and Jordan for this one.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@682 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-05-09 21:48:28 +00:00
commit dc231a7041
2 changed files with 4 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

4
mainboard/pcengines/alix1c/dts
View file

@ -36,9 +36,9 @@
/config/("southbridge/amd/cs5536/dts");
/* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */
lpc_serirq_enable = "0x000010da";
lpc_serirq_enable = "0x0000105A";
/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
lpc_serirq_polarity = "0x0000EF25";
lpc_serirq_polarity = "0x0000EFA5";
/* 0:continuous 1:quiet */
lpc_serirq_mode = "1";
/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.

4
mainboard/pcengines/alix2c3/dts
View file

@ -34,9 +34,9 @@
/config/("southbridge/amd/cs5536/dts");
/* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */
lpc_serirq_enable = "0x000010da";
lpc_serirq_enable = "0x0000105A";
/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
lpc_serirq_polarity = "0x0000EF25";
lpc_serirq_polarity = "0x0000EFA5";
/* 0:continuous 1:quiet */
lpc_serirq_mode = "1";
/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.