- Bump the LinuxBIOS major version
- Rename chip_config chip_operations throughout the tree - Fix Config.lb on most of the Opteron Ports - Fix the amd 8000 chipset support for setting the subsystem vendor and device ids - Add detection of devices that are on the motherboard (i.e. In Config.lb) - Baby step in getting the resource limit handling correct, Ignore fixed resources - Only call enable_childrens_resources on devices we know will have children For some busses like i2c it is non-sense and we don't want it. - Set the resource limits for pnp devices resources. - Improve the resource size detection for pnp devices. - Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels - Added a header file to hold the prototype of isa_dma_init - Fixed most of the superio chips so the should work now, the via superio pci device is the exception. - The code compiles and runs so it is time for me to go to bed. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
parent
f3aa4707d3
commit
dbec2d4090
107 changed files with 1368 additions and 1540 deletions
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@ -251,104 +251,117 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
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dir /pc80
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config chip.h
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northbridge amd/amdk8 "mc0"
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pci 0:18.0
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pci 0:18.0
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pci 0:18.0
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pci 0:18.1
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pci 0:18.2
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pci 0:18.3
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southbridge amd/amd8111 "amd8111" link 2
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pci 0:0.0
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pci 0:1.0 on
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pci 0:1.1 on
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pci 0:1.2 on
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pci 0:1.3 on
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pci 0:1.5 on
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pci 0:1.6 on
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pci 1:0.0 on
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pci 1:0.1 on
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pci 1:0.2 on
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pci 1:1.0 on
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superio NSC/pc87360 link 1
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pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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pnp 2e.2 off # Com 2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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pnp 2e.3 on # Com 1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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pnp 2e.4 off # SWC
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pnp 2e.5 off # Mouse
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pnp 2e.6 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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pnp 2e.7 off # GPIO
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pnp 2e.8 off # ACB
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pnp 2e.9 off # FSCM
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pnp 2e.a off # WDT
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chip northbridge/amd/amdk8 # mc0
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device pci_domain 0 on
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device pci 18.0 on end
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device pci 18.0 on end
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device pci 18.0
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chip southbridge amd/amd8111
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device pci 0:0.0 on
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 0.2 on end
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device pci 1.0 on end
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end
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device pci 1.0 on
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chip superio/NSC/pc87360
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 off # Com 2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # Com 1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.4 off end # SWC
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device pnp 2e.5 off end # Mouse
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device pnp 2e.6 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.7 off end # GPIO
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device pnp 2e.8 off end # ACB
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device pnp 2e.9 off end # FSCM
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device pnp 2e.a off end # WDT
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end
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end
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device pci 1.1 on end
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device pci 1.2 on end
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device pci 1.3 on end
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device pci 1.5 on end
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device pci 1.6 on end
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end
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end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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chip northbridge/amd/amdk8 # mc1
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device pci 19.0 on end
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device pci 19.0 on
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chip southbridge amd/amd8131 # amd8131_0
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 1.0 on end
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device pci 1.1 on end
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end
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chip southbridge amd/amd8131 # amd8131_1
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 1.0 on end
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device pci 1.1 on end
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end
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end
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device pci 19.0 on end
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device pci 19.1 on end
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device pci 19.2 on end
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device pci 19.3 on end
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end
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chip northbridge/amd/amdk8 # mc2
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device pci 1a.0 on end
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device pci 1a.0 on end
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device pci 1a.0 on end
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device pci 1a.1 on end
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device pci 1a.2 on end
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device pci 1a.3 on end
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end
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chip northbridge/amd/amdk8 # mc3
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device pci 1b.0 on end
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device pci 1b.0 on end
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device pci 1b.0 on end
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device pci 1b.1 on end
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device pci 1b.2 on end
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device pci 1b.3 on end
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end
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end # pci_domain 0
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device apic_cluster 0 on
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chip cpu/amd/socket_940
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device apic 0 on end
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end
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chip cpu/amd/socket_940
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device apic 1 on end
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end
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chip cpu/amd/socket_940
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device apic 2 on end
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end
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chip cpu/amd/socket_940
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device apic 3 on end
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end
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end
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end
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northbridge amd/amdk8 "mc1"
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pci 0:19.0
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pci 0:19.0
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pci 0:19.0
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pci 0:19.1
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pci 0:19.2
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pci 0:19.3
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southbridge amd/amd8131 "amd8131_0" link 1
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pci 0:0.0
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pci 0:0.1
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pci 0:1.0
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pci 0:1.1
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end
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southbridge amd/amd8131 "amd8131_1" link 1
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pci 0:0.0
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pci 0:0.1
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pci 0:1.0
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pci 0:1.1
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end
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end
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northbridge amd/amdk8 "mc2"
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pci 0:1a.0
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pci 0:1a.0
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pci 0:1a.0
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pci 0:1a.1
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pci 0:1a.2
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pci 0:1a.3
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end
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northbridge amd/amdk8 "mc3"
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pci 0:1b.0
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pci 0:1b.0
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pci 0:1b.0
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pci 0:1b.1
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pci 0:1b.2
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pci 0:1b.3
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end
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cpu k8 "cpu0"
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end
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cpu k8 "cpu1"
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end
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cpu k8 "cpu2"
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end
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cpu k8 "cpu3"
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end
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##
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## Include the old serial code for those few places that still need it.
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##
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@ -1,4 +1,4 @@
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extern struct chip_control mainboard_amd_quartet_control;
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extern struct chip_operations mainboard_amd_quartet_control;
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struct mainboard_amd_quartet_config {
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int nothing;
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@ -8,37 +8,7 @@
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#include "../../../northbridge/amd/amdk8/northbridge.h"
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#include "chip.h"
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unsigned long initial_apicid[CONFIG_MAX_CPUS] =
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{
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0, 1, 2, 3,
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};
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static struct device_operations mainboard_operations = {
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.read_resources = root_dev_read_resources,
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.set_resources = root_dev_set_resources,
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.enable_resources = enable_childrens_resources,
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.init = 0,
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.scan_bus = amdk8_scan_root_bus,
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.enable = 0,
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};
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static void enumerate(struct chip *chip)
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{
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struct chip *child;
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if (chip->control && chip->control->name) {
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printk_debug("Enumerating: %s\n", chip->control->name);
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}
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dev_root.ops = &mainboard_operations;
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chip->dev = &dev_root;
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chip->bus = 0;
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for (child = chip->children; child; child = child->next) {
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child->bus = &dev_root.link[0];
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}
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}
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struct chip_control mainboard_amd_quartet_control = {
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.enumerate = enumerate,
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struct chip_operations mainboard_amd_quartet_control = {
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.name = "AMD Quartet mainboard ",
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};
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@ -251,78 +251,93 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
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dir /pc80
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config chip.h
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northbridge amd/amdk8 "mc0"
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pci 0:18.0
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pci 0:18.0
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pci 0:18.0
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pci 0:18.1
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pci 0:18.2
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pci 0:18.3
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southbridge amd/amd8131 "amd8131" link 2
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pci 0:0.0
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pci 0:0.1
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pci 0:1.0
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pci 0:1.1
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chip northbridage/amd/amdk8 # mc0
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device pci_domain 0 on
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device pci 18.0 on end # LDT 0
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device pci 18.0 on end # LDT1
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device pci 18.0 on # LDT2
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chip southbridge/amd/amd8131
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# the on/off keyword is mandatory
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 1.0 on end
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device pci 1.1 on end
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end
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chip southbridge/amd/amd8111
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# this "device pci 0.0" is the parent the next one
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# PCI bridge
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device pci 0.0 on
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 0.2 on end
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device pci 1.0 off end
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end
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device pci 1.0 on
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chip superio/windond/w83627hf
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 on # Com 1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off # Com 2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off end # CIR
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device pnp 2e.7 off end # GAM_MIDI_GIPO1
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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end
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end
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end
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device pci 1.1 on end
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device pci 1.2 on end
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device pci 1.3 on end
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device pci 1.5 off end
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device pci 1.6 off end
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end
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end # device pci 18.0
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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chip northbridge/amd/amdk8
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device pci 19.0 on end
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device pci 19.0 on end
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device pci 19.0 on end
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device pci 19.1 on end
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device pci 19.2 on end
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device pci 19.3 on end
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end
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end
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southbridge amd/amd8111 "amd8111" link 2
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#pci 0:0.0
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#pci 0:1.0 on
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#pci 0:1.1 on
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#pci 0:1.2 on
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#pci 0:1.3 on
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#pci 0:1.5 off
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#pci 0:1.6 off
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#pci 1:0.0 on
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#pci 1:0.1 on
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#pci 1:0.2 on
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#pci 1:1.0 off
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superio winbond/w83627hf link 1
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pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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pnp 2e.3 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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pnp 2e.6 off # CIR
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pnp 2e.7 off # GAME_MIDI_GIPO1
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pnp 2e.8 off # GPIO2
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pnp 2e.9 off # GPIO3
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pnp 2e.a off # ACPI
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pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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end
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device apci_cluster 0 on
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chip cpu/amd/socket_940
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device apic 0 on end
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end
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chip cpu/amd/socket_940
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device apic 1 on end
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end
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end
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end
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northbridge amd/amdk8 "mc1"
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pci 0:19.0
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pci 0:19.0
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pci 0:19.0
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pci 0:19.1
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pci 0:19.2
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pci 0:19.3
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end
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cpu k8 "cpu0"
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register "ldt2" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
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end
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cpu k8 "cpu1"
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end
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##
|
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## Include the old serial code for those few places that still need it.
|
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##
|
||||
|
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@ -1,4 +1,4 @@
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extern struct chip_control mainboard_amd_serenade_control;
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extern struct chip_operations mainboard_amd_serenade_control;
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struct mainboard_amd_serenade_config {
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int nothing;
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@ -8,37 +8,6 @@
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#include "../../../northbridge/amd/amdk8/northbridge.h"
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#include "chip.h"
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unsigned long initial_apicid[CONFIG_MAX_CPUS] =
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{
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0, 1,
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};
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static struct device_operations mainboard_operations = {
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.read_resources = root_dev_read_resources,
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.set_resources = root_dev_set_resources,
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.enable_resources = enable_childrens_resources,
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||||
.init = 0,
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.scan_bus = amdk8_scan_root_bus,
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.enable = 0,
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||||
};
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||||
|
||||
static void enumerate(struct chip *chip)
|
||||
{
|
||||
struct chip *child;
|
||||
|
||||
if (chip->control && chip->control->name) {
|
||||
printk_debug("Enumerating: %s\n", chip->control->name);
|
||||
}
|
||||
|
||||
dev_root.ops = &mainboard_operations;
|
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chip->dev = &dev_root;
|
||||
chip->bus = 0;
|
||||
for (child = chip->children; child; child = child->next) {
|
||||
child->bus = &dev_root.link[0];
|
||||
}
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||||
}
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||||
|
||||
struct chip_control mainboard_amd_serenade_control = {
|
||||
.enumerate = enumerate,
|
||||
struct chip_operations mainboard_amd_serenade_control = {
|
||||
.name = "AMD Serenade mainboard ",
|
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};
|
||||
|
|
|
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|
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@ -1,4 +1,4 @@
|
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extern struct chip_control mainboard_amd_solo_control;
|
||||
extern struct chip_operations mainboard_amd_solo_control;
|
||||
|
||||
struct mainboard_amd_solo_config {
|
||||
int nothing;
|
||||
|
|
|
|||
|
|
@ -10,30 +10,6 @@
|
|||
#include "chip.h"
|
||||
|
||||
|
||||
unsigned long initial_apicid[CONFIG_MAX_CPUS] = {
|
||||
0,
|
||||
};
|
||||
|
||||
static struct device_operations mainboard_operations = {
|
||||
.read_resources = root_dev_read_resources,
|
||||
.set_resources = root_dev_set_resources,
|
||||
.enable_resources = enable_childrens_resources,
|
||||
.init = 0,
|
||||
.scan_bus = amdk8_scan_root_bus,
|
||||
.enable = 0,
|
||||
};
|
||||
|
||||
static void enumerate(struct chip *chip)
|
||||
{
|
||||
struct chip *child;
|
||||
dev_root.ops = &mainboard_operations;
|
||||
chip->dev = &dev_root;
|
||||
chip->bus = 0;
|
||||
for (child = chip->children; child; child = child->next) {
|
||||
child->bus = &dev_root.link[0];
|
||||
}
|
||||
}
|
||||
struct chip_control mainboard_amd_solo_control = {
|
||||
.enumerate = enumerate,
|
||||
struct chip_operations mainboard_amd_solo_control = {
|
||||
.name = "AMD Solo7 mainboard ",
|
||||
};
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue