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- Bump the LinuxBIOS major version

Browse source 
- Rename chip_config chip_operations throughout the tree
- Fix Config.lb on most of the Opteron Ports
- Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
- Add detection of devices that are on the motherboard (i.e. In Config.lb)
- Baby step in getting the resource limit handling correct, Ignore fixed resources
- Only call enable_childrens_resources on devices we know will have children
  For some busses like i2c it is non-sense and we don't want it.
- Set the resource limits for pnp devices resources.
- Improve the resource size detection for pnp devices.
- Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
- Added a header file to hold the prototype of isa_dma_init
- Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
- The code compiles and runs so it is time for me to go to bed.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman 2004-10-21 10:44:08 +00:00
commit dbec2d4090
107 changed files with 1368 additions and 1540 deletions
Download patch file Download diff file Expand all files Collapse all files

173
src/mainboard/Iwill/DK8S2/Config.lb
View file

@ -242,95 +242,92 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
dir /pc80
config chip.h
northbridge amd/amdk8 "mc0"
pci 0:18.0
pci 0:18.0
pci 0:18.0
pci 0:18.1
pci 0:18.2
pci 0:18.3
southbridge amd/amd8131 "amd8131" link 0
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
chip northbridge/amd/amdk8
device pci_domain 0 on
device pci 18.0 on # LDT 0
chip southbridge/amd/amd8131
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
chip southbridge/amd/amd8111
# this "device pci 0.0" is the parent the next one
# PCI bridge
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 on end
device pci 1.0 off end
end
device pci 1.0 on
chip superio/winbond/w83627hf
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
register "com1" = "{1}"
# register "com1" = "{1, 0, 0x3f8, 4}"
# register "lpt" = "{1}"
end
end
device pci 1.1 on end
device pci 1.2 on end
device pci 1.3 on end
device pci 1.5 off end
device pci 1.6 off end
end
end # LDT0
device pci 18.0 on end # LDT1
device pci 18.0 on end # LDT2
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
chip northbridge/amd/amdk8
device pci 19.0 on end
device pci 19.0 on end
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
end
device apic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
end
end
southbridge amd/amd8111 "amd8111" link 0
pci 0:0.0
pci 0:1.0 on
pci 0:1.1 on
pci 0:1.2 on
pci 0:1.3 on
pci 0:1.5 off
pci 0:1.6 off
pci 1:0.0 on
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 off
superio winbond/w83627hf link 1
pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
pnp 2e.6 off # CIR
pnp 2e.7 off # GAME_MIDI_GIPO1
pnp 2e.8 off # GPIO2
pnp 2e.9 off # GPIO3
pnp 2e.a off # ACPI
pnp 2e.b on # HW Monitor
io 0x60 = 0x290
register "com1" = "{1}"
# register "com1" = "{1, 0, 0x3f8, 4}"
# register "lpt" = "{1}"
end
# superio winbond/w83627hf link 1
# pnp 2e.0
# pnp 2e.1
# pnp 2e.2
# pnp 2e.3
# pnp 2e.4
# pnp 2e.5
# pnp 2e.6
# pnp 2e.7
# pnp 2e.8
# pnp 2e.9
# pnp 2e.a
# register "com1" = "{1, 0, 0x3f8, 4}"
# register "lpt" = "{1}"
# end
end
end
northbridge amd/amdk8 "mc1"
pci 0:19.0
pci 0:19.0
pci 0:19.0
pci 0:19.1
pci 0:19.2
pci 0:19.3
end
cpu k8 "cpu0"
register "ldt0" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
end
cpu k8 "cpu1"
end
##

2
src/mainboard/Iwill/DK8S2/chip.h
View file

@ -1,4 +1,4 @@
extern struct chip_control mainboard_Iwill_DK8S2_control;
extern struct chip_operations mainboard_Iwill_DK8S2_control;
struct mainboard_Iwill_DK8S2_config {
int nothing;

26
src/mainboard/Iwill/DK8S2/mainboard.c
View file

@ -9,31 +9,7 @@
#include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1,
};
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = amdk8_scan_root_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
}
struct chip_control mainboard_Iwill_DK8S2_control = {
struct chip_operations mainboard_Iwill_DK8S2_control = {
.enumerate = enumerate,
.name = "Iwill DK8S2 mainboard ",
};

118
src/mainboard/Iwill/DK8X/Config.lb
View file

@ -239,65 +239,73 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
dir /pc80
config chip.h
northbridge amd/amdk8 "mc0"
pci 0:18.0
pci 0:18.0
pci 0:18.0
pci 0:18.1
pci 0:18.2
pci 0:18.3
southbridge amd/amd8131 "amd8131" link 0
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
end
southbridge amd/amd8111 "amd8111" link 0
pci 0:0.0
pci 0:1.0 on
pci 0:1.1 on
pci 0:1.2 on
pci 0:1.3 on
pci 0:1.5 off
pci 0:1.6 off
pci 1:0.0 on
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 off
superio winbond/w83627thf link 1
pnp 2e.0
pnp 2e.1
pnp 2e.2
pnp 2e.3
pnp 2e.4
pnp 2e.5
pnp 2e.6
pnp 2e.7
pnp 2e.8
pnp 2e.9
pnp 2e.a
register "com1" = "{1, 0, 0x3f8, 4}"
register "lpt" = "{1}"
chip northbridge/amd/amdk8
device pci_domain 0 on
device pci 18.0 on # northbridge
# devices on link 0, link 0 == LDT 0
chip southbridge/amd/amd8131
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
chip southbridge/amd/amd8111
# this "device pci 0.0" is the parent the next one
# PCI bridge
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 on end
device pci 1.0 off end
end
device pci 1.0 on
chip superio/winbond/w83627thf
device pnp 2e.0 on end
device pnp 2e.1 on end
device pnp 2e.2 on end
device pnp 2e.3 on end
device pnp 2e.4 on end
device pnp 2e.5 on end
device pnp 2e.6 on end
device pnp 2e.7 on end
device pnp 2e.8 on end
device pnp 2e.9 on end
device pnp 2e.a on end
end
end
device pci 1.1 on end
device pci 1.2 on end
device pci 1.3 on end
device pci 1.5 off end
device pci 1.6 off end
end
end # LDT0
device pci 18.0 on end # LDT1
device pci 18.0 on end # LDT2
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
chip northbridge/amd/amdk8
device pci 19.0 on end
device pci 19.0 on end
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
end
device apic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
end
end
end
northbridge amd/amdk8 "mc1"
pci 0:19.0
pci 0:19.0
pci 0:19.0
pci 0:19.1
pci 0:19.2
pci 0:19.3
end
cpu k8 "cpu0"
register "ldt0" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
end
cpu k8 "cpu1"
end
##
## Include the old serial code for those few places that still need it.
##

2
src/mainboard/Iwill/DK8X/chip.h
View file

@ -1,4 +1,4 @@
extern struct chip_control mainboard_arima_hdama_control;
extern struct chip_operations mainboard_arima_hdama_control;
struct mainboard_arima_hdama_config {
int nothing;

28
src/mainboard/Iwill/DK8X/mainboard.c
View file

@ -8,33 +8,7 @@
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1,
};
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = amdk8_scan_root_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
}
struct chip_control mainboard_arima_hdama_control = {
.enumerate = enumerate,
struct chip_operations mainboard_arima_hdama_control = {
.name = "Arima HDAMA mainboard ",
};

201
src/mainboard/amd/quartet/Config.lb
View file

@ -251,104 +251,117 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
dir /pc80
config chip.h
northbridge amd/amdk8 "mc0"
pci 0:18.0
pci 0:18.0
pci 0:18.0
pci 0:18.1
pci 0:18.2
pci 0:18.3
southbridge amd/amd8111 "amd8111" link 2
pci 0:0.0
pci 0:1.0 on
pci 0:1.1 on
pci 0:1.2 on
pci 0:1.3 on
pci 0:1.5 on
pci 0:1.6 on
pci 1:0.0 on
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 on
superio NSC/pc87360 link 1
pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.3 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.4 off # SWC
pnp 2e.5 off # Mouse
pnp 2e.6 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
pnp 2e.7 off # GPIO
pnp 2e.8 off # ACB
pnp 2e.9 off # FSCM
pnp 2e.a off # WDT
chip northbridge/amd/amdk8 # mc0
device pci_domain 0 on
device pci 18.0 on end
device pci 18.0 on end
device pci 18.0
chip southbridge amd/amd8111
device pci 0:0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 on end
device pci 1.0 on end
end
device pci 1.0 on
chip superio/NSC/pc87360
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.4 off end # SWC
device pnp 2e.5 off end # Mouse
device pnp 2e.6 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 2e.7 off end # GPIO
device pnp 2e.8 off end # ACB
device pnp 2e.9 off end # FSCM
device pnp 2e.a off end # WDT
end
end
device pci 1.1 on end
device pci 1.2 on end
device pci 1.3 on end
device pci 1.5 on end
device pci 1.6 on end
end
end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
chip northbridge/amd/amdk8 # mc1
device pci 19.0 on end
device pci 19.0 on
chip southbridge amd/amd8131 # amd8131_0
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
chip southbridge amd/amd8131 # amd8131_1
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
end
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
chip northbridge/amd/amdk8 # mc2
device pci 1a.0 on end
device pci 1a.0 on end
device pci 1a.0 on end
device pci 1a.1 on end
device pci 1a.2 on end
device pci 1a.3 on end
end
chip northbridge/amd/amdk8 # mc3
device pci 1b.0 on end
device pci 1b.0 on end
device pci 1b.0 on end
device pci 1b.1 on end
device pci 1b.2 on end
device pci 1b.3 on end
end
end # pci_domain 0
device apic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
end
chip cpu/amd/socket_940
device apic 2 on end
end
chip cpu/amd/socket_940
device apic 3 on end
end
end
end
northbridge amd/amdk8 "mc1"
pci 0:19.0
pci 0:19.0
pci 0:19.0
pci 0:19.1
pci 0:19.2
pci 0:19.3
southbridge amd/amd8131 "amd8131_0" link 1
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
end
southbridge amd/amd8131 "amd8131_1" link 1
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
end
end
northbridge amd/amdk8 "mc2"
pci 0:1a.0
pci 0:1a.0
pci 0:1a.0
pci 0:1a.1
pci 0:1a.2
pci 0:1a.3
end
northbridge amd/amdk8 "mc3"
pci 0:1b.0
pci 0:1b.0
pci 0:1b.0
pci 0:1b.1
pci 0:1b.2
pci 0:1b.3
end
cpu k8 "cpu0"
end
cpu k8 "cpu1"
end
cpu k8 "cpu2"
end
cpu k8 "cpu3"
end
##
## Include the old serial code for those few places that still need it.
##

2
src/mainboard/amd/quartet/chip.h
View file

@ -1,4 +1,4 @@
extern struct chip_control mainboard_amd_quartet_control;
extern struct chip_operations mainboard_amd_quartet_control;
struct mainboard_amd_quartet_config {
int nothing;

32
src/mainboard/amd/quartet/mainboard.c
View file

@ -8,37 +8,7 @@
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1, 2, 3,
};
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = amdk8_scan_root_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
{
struct chip *child;
if (chip->control && chip->control->name) {
printk_debug("Enumerating: %s\n", chip->control->name);
}
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for (child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
}
struct chip_control mainboard_amd_quartet_control = {
.enumerate = enumerate,
struct chip_operations mainboard_amd_quartet_control = {
.name = "AMD Quartet mainboard ",
};

151
src/mainboard/amd/serenade/Config.lb
View file

@ -251,78 +251,93 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
dir /pc80
config chip.h
northbridge amd/amdk8 "mc0"
pci 0:18.0
pci 0:18.0
pci 0:18.0
pci 0:18.1
pci 0:18.2
pci 0:18.3
southbridge amd/amd8131 "amd8131" link 2
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
chip northbridage/amd/amdk8 # mc0
device pci_domain 0 on
device pci 18.0 on end # LDT 0
device pci 18.0 on end # LDT1
device pci 18.0 on # LDT2
chip southbridge/amd/amd8131
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
chip southbridge/amd/amd8111
# this "device pci 0.0" is the parent the next one
# PCI bridge
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 on end
device pci 1.0 off end
end
device pci 1.0 on
chip superio/windond/w83627hf
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAM_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
end
end
device pci 1.1 on end
device pci 1.2 on end
device pci 1.3 on end
device pci 1.5 off end
device pci 1.6 off end
end
end # device pci 18.0
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
chip northbridge/amd/amdk8
device pci 19.0 on end
device pci 19.0 on end
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
end
southbridge amd/amd8111 "amd8111" link 2
#pci 0:0.0
#pci 0:1.0 on
#pci 0:1.1 on
#pci 0:1.2 on
#pci 0:1.3 on
#pci 0:1.5 off
#pci 0:1.6 off
#pci 1:0.0 on
#pci 1:0.1 on
#pci 1:0.2 on
#pci 1:1.0 off
superio winbond/w83627hf link 1
pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
pnp 2e.6 off # CIR
pnp 2e.7 off # GAME_MIDI_GIPO1
pnp 2e.8 off # GPIO2
pnp 2e.9 off # GPIO3
pnp 2e.a off # ACPI
pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
device apci_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
end
end
end
northbridge amd/amdk8 "mc1"
pci 0:19.0
pci 0:19.0
pci 0:19.0
pci 0:19.1
pci 0:19.2
pci 0:19.3
end
cpu k8 "cpu0"
register "ldt2" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
end
cpu k8 "cpu1"
end
##
## Include the old serial code for those few places that still need it.
##

2
src/mainboard/amd/serenade/chip.h
View file

@ -1,4 +1,4 @@
extern struct chip_control mainboard_amd_serenade_control;
extern struct chip_operations mainboard_amd_serenade_control;
struct mainboard_amd_serenade_config {
int nothing;

33
src/mainboard/amd/serenade/mainboard.c
View file

@ -8,37 +8,6 @@
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1,
};
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = amdk8_scan_root_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
{
struct chip *child;
if (chip->control && chip->control->name) {
printk_debug("Enumerating: %s\n", chip->control->name);
}
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for (child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
}
struct chip_control mainboard_amd_serenade_control = {
.enumerate = enumerate,
struct chip_operations mainboard_amd_serenade_control = {
.name = "AMD Serenade mainboard ",
};

2
src/mainboard/amd/solo/chip.h
View file

@ -1,4 +1,4 @@
extern struct chip_control mainboard_amd_solo_control;
extern struct chip_operations mainboard_amd_solo_control;
struct mainboard_amd_solo_config {
int nothing;

26
src/mainboard/amd/solo/mainboard.c
View file

@ -10,30 +10,6 @@
#include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] = {
0,
};
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = amdk8_scan_root_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for (child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
}
struct chip_control mainboard_amd_solo_control = {
.enumerate = enumerate,
struct chip_operations mainboard_amd_solo_control = {
.name = "AMD Solo7 mainboard ",
};

6
src/mainboard/arima/hdama/Config.lb
View file

@ -123,7 +123,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc
dir /pc80
config chip.h
# sample config for arima/hdama
# config for arima/hdama
chip northbridge/amd/amdk8
device pci_domain 0 on
device pci 18.0 on # northbridge
@ -141,7 +141,7 @@ chip northbridge/amd/amdk8
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 on end
device pci 0.2 off end
device pci 1.0 off end
end
device pci 1.0 on
@ -218,6 +218,8 @@ chip northbridge/amd/amdk8
end
device pci 1.5 off end
device pci 1.6 on end
register "ide0_enable" = "1"
register "ide1_enable" = "1"
end
end # device pci 18.0

7
src/mainboard/arima/hdama/Options.lb
View file

@ -29,9 +29,11 @@ uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
@ -117,6 +119,9 @@ default CONFIG_IOAPIC=1
##
default MAINBOARD_PART_NUMBER="HDAMA"
default MAINBOARD_VENDOR="ARIMA"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
###
### LinuxBIOS layout values

2
src/mainboard/arima/hdama/mainboard.c
View file

@ -313,7 +313,7 @@ static struct device_operations mainboard_operations = {
static void enable_dev(struct device *dev)
{
dev_root.ops = &mainboard_operations;
dev->ops = &mainboard_operations;
}
struct chip_operations mainboard_arima_hdama_ops = {
.name = "Arima HDAMA mainboard ",

2
src/mainboard/densitron/dpx114/chip.h
View file

@ -1,4 +1,4 @@
extern struct chip_control mainboard_densitron_dpx114_control;
extern struct chip_operations mainboard_densitron_dpx114_control;
struct mainboard_densitron_dpx114_config {
int nothing;

20
src/mainboard/densitron/dpx114/mainboard.c
View file

@ -20,24 +20,18 @@ mainboard_scan_bus(device_t root, int maxbus)
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
static void enable_dev(device_t dev)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
dev->ops = &mainboard_operations;
}
struct chip_control mainboard_via_epia_control = {
.enumerate = enumerate,
.name = "VIA EPIA mainboard ",
struct chip_operations mainboard_via_epia_control = {
.enable_dev = enable_dev,
.name = "VIA EPIA mainboard ",
};

2
src/mainboard/digitallogic/adl855pc/chip.h
View file

@ -1,4 +1,4 @@
extern struct chip_control mainboard_digitallogic_adl855pc_control;
extern struct chip_operations mainboard_digitallogic_adl855pc_control;
struct mainboard_digitallogic_adl855pc_config {
int nothing;

20
src/mainboard/digitallogic/adl855pc/mainboard.c
View file

@ -20,24 +20,18 @@ mainboard_scan_bus(device_t root, int maxbus)
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
static void enable_dev(device_t dev)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
dev->ops = &mainboard_operations;
}
struct chip_control mainboard_digitallogic_adl855pc_control = {
.enumerate = enumerate,
.name = "Digital Logic ADL855PC mainboard ",
struct chip_operations mainboard_digitallogic_adl855pc_control = {
.enable_dev = enable_dev,
.name = "Digital Logic ADL855PC mainboard ",
};

2
src/mainboard/emulation/qemu-i386/chip.h
View file

@ -1,4 +1,4 @@
extern struct chip_control mainboard_emulation_qemu_i386_control;
extern struct chip_operations mainboard_emulation_qemu_i386_control;
struct mainboard_emulation_qemu_i386_config {
int nothing;

26
src/mainboard/emulation/qemu-i386/mainboard.c
View file

@ -7,11 +7,6 @@
#include <arch/io.h>
#include "chip.h"
void cpufixup(unsigned long mem)
{
printk_spew("Welcome to LinuxBIOS CPU fixup. done.\n");
}
static int mainboard_scan_bus(device_t root, int maxbus)
{
int retval;
@ -24,25 +19,18 @@ static int mainboard_scan_bus(device_t root, int maxbus)
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
static void enable_dev(struct device *dev)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
dev->ops = &mainboard_operations;
}
struct chip_control mainboard_emulation_qemu_i386_control = {
.enumerate = enumerate,
.name = "qemu mainboard ",
struct chip_operations mainboard_emulation_qemu_i386_control = {
.enable_dev = enable_dev,
.name = "qemu mainboard ",
};

142
src/mainboard/ibm/e325/Config.lb
View file

@ -251,75 +251,87 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
dir /pc80
config chip.h
northbridge amd/amdk8 "mc0"
pci 0:18.0
pci 0:18.0
pci 0:18.0
pci 0:18.1
pci 0:18.2
pci 0:18.3
southbridge amd/amd8131 "amd8131" link 1
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
end
southbridge amd/amd8111 "amd8111" link 1
pci 0:0.0
pci 0:1.0 on
pci 0:1.1 on
pci 0:1.2 on
pci 0:1.3 on
pci 0:1.5 off
pci 0:1.6 off
pci 1:0.0 on
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 off
superio NSC/pc87366 link 1
pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.3 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.4 off # SWC
pnp 2e.5 off # Mouse
pnp 2e.6 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
pnp 2e.7 off # GPIO
pnp 2e.8 off # ACB
pnp 2e.9 off # FSCM
pnp 2e.a off # WDT
chip northbridge/amd/amdk8
device pci_domain 0 on
device pci 18.0 on end # LDT 0
device pci 18.0 on # LDT 1
chip southbridge/amd/amd8131
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
chip southbridge/amd/amd8111
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 on end
device pci 1.0 off end
end
device pci 1.0 on
chip superio/NSC/pc87366
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.4 off end # SWC
device pnp 2e.5 off end # Mouse
device pnp 2e.6 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 2e.7 off end # GPIO
device pnp 2e.8 off end # ACB
device pnp 2e.9 off end # FSCM
device pnp 2e.a off end # WDT
end
end
device pci 1.1 on end
device pci 1.2 on end
device pci 1.3 on end
device pci 1.5 off end
device pci 1.6 off end
end
end # device pci 18.0
device pci 18.0 on end # LDT2
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
chip northbridge/amd/amdk8
device pci 19.0 on end
device pci 19.0 on end
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
end
device apic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
end
end
end
northbridge amd/amdk8 "mc1"
pci 0:19.0
pci 0:19.0
pci 0:19.0
pci 0:19.1
pci 0:19.2
pci 0:19.3
end
cpu k8 "cpu0"
register "ldt1" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
end
cpu k8 "cpu1"
end
##
## Include the old serial code for those few places that still need it.
##

2
src/mainboard/ibm/e325/chip.h
View file

@ -1,4 +1,4 @@
extern struct chip_control mainboard_ibm_e325_control;
extern struct chip_operations mainboard_ibm_e325_control;
struct mainboard_ibm_e325_config {
int nothing;

34
src/mainboard/ibm/e325/mainboard.c
View file

@ -8,38 +8,6 @@
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1,
};
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = amdk8_scan_root_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
{
struct chip *child;
if (chip->control && chip->control->name) {
printk_debug("Enumerating: %s\n", chip->control->name);
}
/* update device operation for dynamic root */
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for (child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
}
struct chip_control mainboard_ibm_e325_control = {
.enumerate = enumerate,
struct chip_operations mainboard_ibm_e325_control = {
.name = "IBM E325 mainboard ",
};

142
src/mainboard/newisys/khepri/Config.lb
View file

@ -253,75 +253,87 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
dir /pc80
config chip.h
northbridge amd/amdk8 "mc0"
pci 0:18.0
pci 0:18.0
pci 0:18.0
pci 0:18.1
pci 0:18.2
pci 0:18.3
southbridge amd/amd8131 "amd8131" link 1
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
end
southbridge amd/amd8111 "amd8111" link 1
pci 0:0.0
pci 0:1.0 on
pci 0:1.1 on
pci 0:1.2 on
pci 0:1.3 on
pci 0:1.5 on
pci 0:1.6 on
pci 1:0.0 on
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 on
superio NSC/pc87360 link 1
pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.3 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.4 off # SWC
pnp 2e.5 off # Mouse
pnp 2e.6 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
pnp 2e.7 off # GPIO
pnp 2e.8 off # ACB
pnp 2e.9 off # FSCM
pnp 2e.a off # WDT
chip northbridge/amd/amdk8
device pci_domain 0 on
device pci 18.0 on end # LDT 0
device pci 18.0 on # LDT 1
chip southbridge/amd/amd8131
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
chip southbridge/amd/amd8111
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 on end
device pci 1.0 on end
end
device pci 1.0 on
chip superio/NSC/pc87360
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.4 off end # SWC
device pnp 2e.5 off end # Mouse
device pnp 2e.6 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 2e.7 off end # GPIO
device pnp 2e.8 off end # ACB
device pnp 2e.9 off end # FSCM
device pnp 2e.a off end # WDT
end
end
device pci 1.1 on end
device pci 1.2 on end
device pci 1.3 on end
device pci 1.5 on end
device pci 1.6 on end
end
end # LDT1
device pci 18.0 on end # LDT2
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
chip northbridge/amd/amdk8
device pci 19.0 on end
device pci 19.0 on end
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
end
device apic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
end
end
end
northbridge amd/amdk8 "mc1"
pci 0:19.0
pci 0:19.0
pci 0:19.0
pci 0:19.1
pci 0:19.2
pci 0:19.3
end
cpu k8 "cpu0"
register "ldt1" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
end
cpu k8 "cpu1"
end
##
## Include the old serial code for those few places that still need it.
##

2
src/mainboard/newisys/khepri/chip.h
View file

@ -1,4 +1,4 @@
extern struct chip_control mainboard_newisys_khepri_control;
extern struct chip_operations mainboard_newisys_khepri_control;
struct mainboard_newisys_khepri_config {
int nothing;

28
src/mainboard/newisys/khepri/mainboard.c
View file

@ -8,33 +8,7 @@
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1,
};
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = amdk8_scan_root_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
}
struct chip_control mainboard_newisys_khepri_control = {
.enumerate = enumerate,
struct chip_operations mainboard_newisys_khepri_control = {
.name = "Newisys Khepri mainboard ",
};

15
src/mainboard/technologic/ts5300/Config.lb
View file

@ -210,22 +210,13 @@ mainboardinit ./auto.inc
dir /pc80
config chip.h
northbridge amd/sc520 "elan_nb"
southbridge amd/sc520 "elan_sb"
chip northbridge/amd/sc520
chip southbridge amd/sc520
register "enable_usb" = "0"
register "enable_native_ide" = "1"
register "enable_com_ports" = "1"
register "enable_keyboard" = "0"
register "enable_nvram" = "1"
end
chip cpu/amd/sc520
end
cpu p6 "cpu0"
end
##
## Include the old serial code for those few places that still need it.
##
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc

2
src/mainboard/technologic/ts5300/chip.h
View file

@ -1,4 +1,4 @@
extern struct chip_control mainboard_technologic_ts5300_control;
extern struct chip_operations mainboard_technologic_ts5300_control;
struct mainboard_technologic_ts5300_config {
int nothing;

22
src/mainboard/technologic/ts5300/mainboard.c
View file

@ -20,24 +20,18 @@ mainboard_scan_bus(device_t root, int maxbus)
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
static void enable_dev(device_t dev)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
dev->ops = &mainbaord_operations;
}
struct chip_control mainboard_technologic_ts5300_control = {
.enumerate = enumerate,
.name = "Technologic Systems TS5300 mainboard ",
struct chip_operations mainboard_technologic_ts5300_control = {
.enable_dev = enable_dev,
.name = "Technologic Systems TS5300 mainboard ",
};

136
src/mainboard/tyan/s2735/Config.lb
View file

@ -152,71 +152,79 @@ mainboardinit cpu/p6/disable_mmx_sse.inc
config chip.h
northbridge intel/e7501 "e7501"
pci 0:2.0
pci 0:0.0
pci 0:0.1
pci 0:6.0
southbridge intel/i82870 "i82870"
pci 0:1c.0
pci 0:1d.0
pci 0:1e.0
pci 0:1f.0
chip northbridge/intel/e7501
device pci_domain 0
device pci 0.0 on end
device pci 0.1 on end
device pci 2.0 on
chip southbridge/intel/i82870
device pci 1c.0
device pci 1d.0
device pci 1e.0
device pci 1f.0
end
end
device pci 6.0 on end
chip southbridge/intel/i82801er
device pci 1d.0 on end
device pci 1d.1 on end
device pci 1d.2 on end
device pci 1d.3 on end
device pci 1d.7 on end
device pci 1e.0 on end
device pci 1f.0 on
# device pci 8.0 end
chip winbond/w83627hf
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
end
end
device pci 1f.1 off end
device pci 1f.2 on end
device pci 1f.3 on end
device pci 1f.5 off end
device pci 1f.6 off end
end
end
device apic_cluster 0
chip cpu/intel/socket_mPGA604_533Mhz
apic 0
end
chip cpu/intel/socket_mPGA604_533Mhz
apic 6
end
end
end
southbridge intel/i82801er "i82801er"
pci 0:1f.0
pci 0:1d.0 on
pci 0:1d.1 on
pci 0:1d.2 on
pci 0:1d.3 on
pci 0:1d.7 on
pci 0:1e.0 on
pci 0:1f.1 off
pci 0:1f.2 on
pci 0:1f.3 on
pci 0:1f.5 off
pci 0:1f.6 off
# pci 1:8.0 off
superio winbond/w83627hf
pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
pnp 2e.6 off # CIR
pnp 2e.7 off # GAME_MIDI_GIPO1
pnp 2e.8 off # GPIO2
pnp 2e.9 off # GPIO3
pnp 2e.a off # ACPI
pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
end
#end
dir /pc80
#dir /bioscall
cpu p6 "cpu0"
end
cpu p6 "cpu1"
end
cpu p6 "cpu2"
end
cpu p6 "cpu3"
end

2
src/mainboard/tyan/s2735/chip.h
View file

@ -1,4 +1,4 @@
extern struct chip_control mainboard_tyan_s2735_control;
extern struct chip_operations mainboard_tyan_s2735_control;
struct mainboard_tyan_s2735_config {
int fixup_scsi;

49
src/mainboard/tyan/s2735/mainboard.c
View file

@ -6,10 +6,7 @@
#include "chip.h"
//#include <part/mainboard.h>
//#include "lsi_scsi.c"
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 6, 1, 7
};
#if 0
static void fixup_lsi_53c1030(struct device *pdev)
{
@ -122,29 +119,6 @@ static void vga_fixup(void) {
}
*/
static void
enable(struct chip *chip, enum chip_pass pass)
{
struct mainboard_tyan_s2735_config *conf =
(struct mainboard_tyan_s2735_config *)chip->chip_info;
switch (pass) {
default: break;
// case CONF_PASS_PRE_CONSOLE:
// case CONF_PASS_PRE_PCI:
case CONF_PASS_POST_PCI:
case CONF_PASS_PRE_BOOT:
// if (conf->fixup_scsi)
// onboard_scsi_fixup();
// if (conf->fixup_vga)
// vga_fixup();
// printk_debug("mainboard fixup pass %d done\r\n",pass);
break;
}
}
static int
mainboard_scan_bus(device_t root, int maxbus)
{
@ -158,25 +132,18 @@ mainboard_scan_bus(device_t root, int maxbus)
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
static void enable_dev(device_t dev)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
dev->ops = &mainboard_ops;
}
struct chip_control mainboard_tyan_s2735_control = {
.enable = enable,
.enumerate = enumerate,
struct chip_operations mainboard_tyan_s2735_control = {
.enable_dev = enable_dev,
.name = "Tyan s2735 mainboard ",
};

2
src/mainboard/via/epia-m/chip.h
View file

@ -1,4 +1,4 @@
extern struct chip_control mainboard_via_epia_m_control;
extern struct chip_operations mainboard_via_epia_m_control;
struct mainboard_via_epia_m_config {
int nothing;

45
src/mainboard/via/epia-m/mainboard.c
View file

@ -47,51 +47,22 @@ void write_protect_vgabios(void)
}
static void
enable(struct chip *chip, enum chip_pass pass)
{
struct mainboard_tyan_s4882_config *conf =
(struct mainboard_tyan_s4882_config *)chip->chip_info;
switch (pass) {
default: break;
// case CONF_PASS_PRE_CONSOLE:
// case CONF_PASS_PRE_PCI:
case CONF_PASS_POST_PCI:
// case CONF_PASS_PRE_BOOT:
// if (conf->fixup_scsi)
// onboard_scsi_fixup();
// if (conf->fixup_vga)
// vga_fixup();
printk_debug("mainboard fixup pass %d done\r\n",
pass);
break;
}
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
static void enable_dev(device_t dev)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
dev->ops = &mainboard_operations;
}
struct chip_control mainboard_via_epia_m_control = {
.enumerate = enumerate,
.name = "VIA EPIA-M mainboard ",
.enable = enable
struct chip_operations mainboard_via_epia_m_control = {
.enable_dev = enable_dev,
.name = "VIA EPIA-M mainboard ",
};

2
src/mainboard/via/epia/chip.h
View file

@ -1,4 +1,4 @@
extern struct chip_control mainboard_via_epia_control;
extern struct chip_operations mainboard_via_epia_control;
struct mainboard_via_epia_config {
int nothing;

21
src/mainboard/via/epia/mainboard.c
View file

@ -20,24 +20,19 @@ mainboard_scan_bus(device_t root, int maxbus)
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
static void enable_dev(device_t dev)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
dev->ops = &mainboard_operations;
}
struct chip_control mainboard_via_epia_control = {
.enumerate = enumerate,
.name = "VIA EPIA mainboard ",
struct chip_operations mainboard_via_epia_control = {
.enable_dev = enable_dev,
.name = "VIA EPIA mainboard ",
};