diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 412ccda4c3..df14a2fe91 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -72,7 +72,7 @@ config SOC_INTEL_PANTHERLAKE_BASE select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC select SOC_INTEL_COMMON_BLOCK_IOC select SOC_INTEL_COMMON_BLOCK_IOE_P2SB - select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_COMMON_BLOCK_IPU if SOC_INTEL_PANTHERLAKE select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_ME_SPEC_21 select SOC_INTEL_COMMON_BLOCK_MEMINIT @@ -231,15 +231,18 @@ endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config MAX_TBT_ROOT_PORTS int + default 2 if SOC_INTEL_WILDCATLAKE default 4 config MAX_ROOT_PORTS int + default 6 if SOC_INTEL_WILDCATLAKE default 10 if SOC_INTEL_PANTHERLAKE_H default 12 config MAX_PCIE_CLOCK_SRC int + default 6 if SOC_INTEL_WILDCATLAKE default 9 config SMM_TSEG_SIZE diff --git a/src/soc/intel/pantherlake/acpi.c b/src/soc/intel/pantherlake/acpi.c index 1c965f411e..0252e1c503 100644 --- a/src/soc/intel/pantherlake/acpi.c +++ b/src/soc/intel/pantherlake/acpi.c @@ -214,12 +214,14 @@ static struct min_sleep_state min_pci_sleep_states[] = { { PCI_DEVFN_PCIE4, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_PCIE5, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_PCIE6, ACPI_DEVICE_SLEEP_D0 }, +#if CONFIG(SOC_INTEL_PANTHERLAKE) { PCI_DEVFN_PCIE7, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_PCIE8, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_PCIE9, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_PCIE10, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_PCIE11, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_PCIE12, ACPI_DEVICE_SLEEP_D0 }, +#endif { PCI_DEVFN_UART0, ACPI_DEVICE_SLEEP_D3 }, { PCI_DEVFN_UART1, ACPI_DEVICE_SLEEP_D3 }, { PCI_DEVFN_GSPI0, ACPI_DEVICE_SLEEP_D3 }, diff --git a/src/soc/intel/pantherlake/chip.c b/src/soc/intel/pantherlake/chip.c index 5fe2a37043..317fa5fa0e 100644 --- a/src/soc/intel/pantherlake/chip.c +++ b/src/soc/intel/pantherlake/chip.c @@ -102,12 +102,14 @@ const char *soc_acpi_name(const struct device *dev) case PCI_DEVFN_PCIE4: return "RP04"; case PCI_DEVFN_PCIE5: return "RP05"; case PCI_DEVFN_PCIE6: return "RP06"; +#if CONFIG(SOC_INTEL_PANTHERLAKE) case PCI_DEVFN_PCIE7: return "RP07"; case PCI_DEVFN_PCIE8: return "RP08"; case PCI_DEVFN_PCIE9: return "RP09"; case PCI_DEVFN_PCIE10: return "RP10"; case PCI_DEVFN_PCIE11: return "RP11"; case PCI_DEVFN_PCIE12: return "RP12"; +#endif case PCI_DEVFN_PMC: return "PMC"; case PCI_DEVFN_UART0: return "UAR0"; case PCI_DEVFN_UART1: return "UAR1"; diff --git a/src/soc/intel/pantherlake/elog.c b/src/soc/intel/pantherlake/elog.c index 7750058be4..5abf766fc7 100644 --- a/src/soc/intel/pantherlake/elog.c +++ b/src/soc/intel/pantherlake/elog.c @@ -36,6 +36,7 @@ static void pch_log_rp_wake_source(void) { PCI_DEVFN_PCIE4, ELOG_WAKE_SOURCE_PME_PCIE4 }, { PCI_DEVFN_PCIE5, ELOG_WAKE_SOURCE_PME_PCIE5 }, { PCI_DEVFN_PCIE6, ELOG_WAKE_SOURCE_PME_PCIE6 }, +#if CONFIG(SOC_INTEL_PANTHERLAKE) { PCI_DEVFN_PCIE7, ELOG_WAKE_SOURCE_PME_PCIE7 }, { PCI_DEVFN_PCIE8, ELOG_WAKE_SOURCE_PME_PCIE8 }, { PCI_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 }, @@ -43,6 +44,7 @@ static void pch_log_rp_wake_source(void) #if CONFIG(SOC_INTEL_PANTHERLAKE_U_H) { PCI_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 }, { PCI_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 }, +#endif #endif }; @@ -62,7 +64,9 @@ static void pch_log_pme_internal_wake_source(void) { PCI_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, { PCI_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI }, { PCI_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI }, +#if CONFIG(SOC_INTEL_PANTHERLAKE) { PCI_DEVFN_TCSS_XDCI, ELOG_WAKE_SOURCE_PME_TCSS_XDCI }, +#endif }; const struct xhci_wake_info xhci_wake_info[] = { { PCI_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index cac866f39a..32be2852db 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -119,6 +119,7 @@ static const struct slot_irq_constraints irq_constraints[] = { FIXED_INT_PIRQ(PCI_DEVFN_DPTF, PCI_INT_A, PIRQ_A), }, }, +#if CONFIG(SOC_INTEL_PANTHERLAKE) { .slot = PCI_DEV_SLOT_IPU, .fns = { @@ -127,14 +128,20 @@ static const struct slot_irq_constraints irq_constraints[] = { FIXED_INT_PIRQ(PCI_DEVFN_IPU, PCI_INT_A, PIRQ_A), }, }, +#endif { .slot = PCI_DEV_SLOT_PCIE_2, .fns = { +#if CONFIG(SOC_INTEL_WILDCATLAKE) + FIXED_INT_PIRQ(PCI_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), +#else FIXED_INT_PIRQ(PCI_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), FIXED_INT_PIRQ(PCI_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), #if CONFIG(SOC_INTEL_PANTHERLAKE_H) FIXED_INT_PIRQ(PCI_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), FIXED_INT_PIRQ(PCI_DEVFN_PCIE12, PCI_INT_D, PIRQ_D), +#endif #endif }, }, @@ -143,8 +150,10 @@ static const struct slot_irq_constraints irq_constraints[] = { .fns = { ANY_PIRQ(PCI_DEVFN_TBT0), ANY_PIRQ(PCI_DEVFN_TBT1), +#if CONFIG(SOC_INTEL_PANTHERLAKE) ANY_PIRQ(PCI_DEVFN_TBT2), ANY_PIRQ(PCI_DEVFN_TBT3), +#endif }, }, { @@ -201,7 +210,7 @@ static const struct slot_irq_constraints irq_constraints[] = { ANY_PIRQ(PCI_DEVFN_CSE_4), }, }, -#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H) +#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_WILDCATLAKE)) { .slot = PCI_DEV_SLOT_UFS, .fns = { @@ -224,10 +233,12 @@ static const struct slot_irq_constraints irq_constraints[] = { FIXED_INT_PIRQ(PCI_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), FIXED_INT_PIRQ(PCI_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), FIXED_INT_PIRQ(PCI_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), +#if CONFIG(SOC_INTEL_PANTHERLAKE) FIXED_INT_PIRQ(PCI_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), FIXED_INT_PIRQ(PCI_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), FIXED_INT_PIRQ(PCI_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), FIXED_INT_PIRQ(PCI_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), +#endif }, }, { diff --git a/src/soc/intel/pantherlake/include/soc/pci_devs.h b/src/soc/intel/pantherlake/include/soc/pci_devs.h index a69f4820c8..dc7130cbb5 100644 --- a/src/soc/intel/pantherlake/include/soc/pci_devs.h +++ b/src/soc/intel/pantherlake/include/soc/pci_devs.h @@ -33,6 +33,12 @@ #define PCI_DEV_IPU _PCI_DEV(IPU, 0) #define PCI_DEV_SLOT_PCIE_2 0x06 +#if CONFIG(SOC_INTEL_WILDCATLAKE) +#define PCI_DEVFN_PCIE5 _PCI_DEVFN(PCIE_2, 0) +#define PCI_DEVFN_PCIE6 _PCI_DEVFN(PCIE_2, 1) +#define PCI_DEV_PCIE5 _PCI_DEV(PCIE_2, 0) +#define PCI_DEV_PCIE6 _PCI_DEV(PCIE_2, 1) +#else #define PCI_DEVFN_PCIE9 _PCI_DEVFN(PCIE_2, 0) #define PCI_DEVFN_PCIE10 _PCI_DEVFN(PCIE_2, 1) #define PCI_DEVFN_PCIE11 _PCI_DEVFN(PCIE_2, 2) @@ -41,6 +47,7 @@ #define PCI_DEV_PCIE10 _PCI_DEV(PCIE_2, 1) #define PCI_DEV_PCIE11 _PCI_DEV(PCIE_2, 2) #define PCI_DEV_PCIE12 _PCI_DEV(PCIE_2, 3) +#endif #define PCI_DEV_SLOT_TBT 0x07 #define PCI_DEVFN_TBT(x) _PCI_DEVFN(TBT, (x)) @@ -48,11 +55,11 @@ #define PCI_DEVFN_TBT0 _PCI_DEVFN(TBT, 0) #define PCI_DEVFN_TBT1 _PCI_DEVFN(TBT, 1) #define PCI_DEVFN_TBT2 _PCI_DEVFN(TBT, 2) -#define PCI_DEVFN_TBT3 _PCI_DEVFN(TBT, 3) +#define PCI_DEVFN_TBT3 _PCI_DEVFN(TBT, 3) #define PCI_DEV_TBT0 _PCI_DEV(TBT, 0) #define PCI_DEV_TBT1 _PCI_DEV(TBT, 1) #define PCI_DEV_TBT2 _PCI_DEV(TBT, 2) -#define PCI_DEV_TBT3 _PCI_DEV(TBT, 3) +#define PCI_DEV_TBT3 _PCI_DEV(TBT, 3) #define PCI_DEV_SLOT_TELEMETRY 0x0a #define PCI_DEVFN_TELEMETRY _PCI_DEVFN(TELEMETRY, 0) @@ -143,7 +150,7 @@ #define PCI_DEV_CSE_3 _PCI_DEV(CSE, 4) #define PCI_DEV_CSE_4 _PCI_DEV(CSE, 5) -#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H) +#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_WILDCATLAKE)) #define PCI_DEV_SLOT_UFS 0x17 #define PCI_DEVFN_UFS _PCI_DEVFN(UFS, 0) #define PCI_DEV_UFS _PCI_DEV(UFS, 0) @@ -170,19 +177,23 @@ #define PCI_DEVFN_PCIE2 _PCI_DEVFN(PCIE_1, 1) #define PCI_DEVFN_PCIE3 _PCI_DEVFN(PCIE_1, 2) #define PCI_DEVFN_PCIE4 _PCI_DEVFN(PCIE_1, 3) +#if CONFIG(SOC_INTEL_PANTHERLAKE) #define PCI_DEVFN_PCIE5 _PCI_DEVFN(PCIE_1, 4) #define PCI_DEVFN_PCIE6 _PCI_DEVFN(PCIE_1, 5) #define PCI_DEVFN_PCIE7 _PCI_DEVFN(PCIE_1, 6) #define PCI_DEVFN_PCIE8 _PCI_DEVFN(PCIE_1, 7) +#endif #define PCI_DEV_PCIE1 _PCI_DEV(PCIE_1, 0) #define PCI_DEV_PCIE2 _PCI_DEV(PCIE_1, 1) #define PCI_DEV_PCIE3 _PCI_DEV(PCIE_1, 2) #define PCI_DEV_PCIE4 _PCI_DEV(PCIE_1, 3) +#if CONFIG(SOC_INTEL_PANTHERLAKE) #define PCI_DEV_PCIE5 _PCI_DEV(PCIE_1, 4) #define PCI_DEV_PCIE6 _PCI_DEV(PCIE_1, 5) #define PCI_DEV_PCIE7 _PCI_DEV(PCIE_1, 6) #define PCI_DEV_PCIE8 _PCI_DEV(PCIE_1, 7) +#endif #define PCI_DEV_SLOT_SIO2 0x1e #define PCI_DEVFN_UART0 _PCI_DEVFN(SIO2, 0) diff --git a/src/soc/intel/pantherlake/pcie_rp.c b/src/soc/intel/pantherlake/pcie_rp.c index 604e7af1b2..cacbab83ad 100644 --- a/src/soc/intel/pantherlake/pcie_rp.c +++ b/src/soc/intel/pantherlake/pcie_rp.c @@ -18,7 +18,11 @@ static const struct pcie_rp_group tbt_rp_groups[] = { }; static const struct pcie_rp_group ptl_rp_groups[] = { +#if CONFIG(SOC_INTEL_WILDCATLAKE) + { .slot = PCI_DEV_SLOT_PCIE_1, .count = 4, .lcap_port_base = 1 }, +#else { .slot = PCI_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, +#endif #if CONFIG(SOC_INTEL_PANTHERLAKE_U_H) { .slot = PCI_DEV_SLOT_PCIE_2, .count = 4, .lcap_port_base = 1 }, #else