From db0f677fd10be05edc7e0d13e36edd643f63784b Mon Sep 17 00:00:00 2001 From: Rui Zhou Date: Wed, 14 Jan 2026 14:09:18 +0800 Subject: [PATCH] mb/google/brox/var/lotso: Add RAM ID for K3KL8L80CM-MGCT Add RAM ID for K3KL8L80CM-MGCT. And importing a single RAM device, so use mb_get_channel_disable_mask to distinguish it. BUG=b/468889066 BRANCH=None TEST=boot to kernel success, and the log shows that the RAM ID is correct. Change-Id: Idc1e890ab826ec008031f54e0fc445fa5ee62978 Signed-off-by: Rui Zhou Reviewed-on: https://review.coreboot.org/c/coreboot/+/90752 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/mainboard/google/brox/Kconfig | 1 + src/mainboard/google/brox/variants/lotso/memory.c | 13 +++++++++++++ .../google/brox/variants/lotso/memory/Makefile.mk | 2 +- .../variants/lotso/memory/dram_id.generated.txt | 3 ++- .../brox/variants/lotso/memory/mem_parts_used.txt | 3 ++- 5 files changed, 19 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index cec63f53be..44db591f32 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -81,6 +81,7 @@ config BOARD_GOOGLE_BROX_EC_ISH config BOARD_GOOGLE_LOTSO select BOARD_GOOGLE_BASEBOARD_BROX select CHROMEOS_WIFI_SAR if CHROMEOS + select ENFORCE_MEM_CHANNEL_DISABLE select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS diff --git a/src/mainboard/google/brox/variants/lotso/memory.c b/src/mainboard/google/brox/variants/lotso/memory.c index 84b9f4a70d..0997707e9f 100644 --- a/src/mainboard/google/brox/variants/lotso/memory.c +++ b/src/mainboard/google/brox/variants/lotso/memory.c @@ -99,6 +99,19 @@ bool variant_is_half_populated(void) return gpio_get(GPP_S0); } +uint8_t mb_get_channel_disable_mask(void) +{ + /* + * GPP_S0 High -> One RAM Chip + * GPP_S0 Low -> Two RAM Chip + * Disable all other channels except first two on each controller + */ + if (gpio_get(GPP_S0)) + return (BIT(2) | BIT(3)); + + return 0; +} + void variant_get_spd_info(struct mem_spd *spd_info) { spd_info->topo = MEM_TOPO_MEMORY_DOWN; diff --git a/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk b/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk index 64f4e227ba..e38115911f 100644 --- a/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk +++ b/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk @@ -7,4 +7,4 @@ SPD_SOURCES = SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 0(0b0000) Parts = K3KL6L60GM-MGCT SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = K3KL8L80DM-MGCU, MT62F1G32D2DS-023 WT:C, H58G56BK8BX068, H58G56CK8BX146, K3KL8L80EM-MGCU -SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = H58G56BK7BX068 +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = H58G56BK7BX068, K3KL8L80CM-MGCT diff --git a/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt index a4824fd008..c27f7926ca 100644 --- a/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt +++ b/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt @@ -9,6 +9,7 @@ H9JCNNNBK3MLYR-N6E 1 (0001) K3KL8L80DM-MGCU 2 (0010) MT62F1G32D2DS-023 WT:C 2 (0010) H58G56BK8BX068 2 (0010) -H58G56BK7BX068 3 (0011) H58G56CK8BX146 2 (0010) K3KL8L80EM-MGCU 2 (0010) +H58G56BK7BX068 3 (0011) +K3KL8L80CM-MGCT 3 (0011) diff --git a/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt index dac8c9957c..7df5ad3b41 100644 --- a/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt +++ b/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt @@ -10,10 +10,11 @@ # Part Name K3KL6L60GM-MGCT +K3KL8L80CM-MGCT H9JCNNNBK3MLYR-N6E K3KL8L80DM-MGCU MT62F1G32D2DS-023 WT:C H58G56BK8BX068 -H58G56BK7BX068 H58G56CK8BX146 K3KL8L80EM-MGCU +H58G56BK7BX068