These changes incorporate steve goodrich'es fixes, and one bug that is
disabled. cs5536: add new entires for SB control etc. cs5536.c: chip_enabled function moved to chip_init, so it only gets run once. IRQ setup improved gx2def.h: new defines added vr.h: new file, with new def's for virtual register control. mainboard config.lb: new entries added for nb and sb control. chipsetinit.c: new controls added -- I forget all the details :-) grphinit.c: new function added northbridge.c: new IRQ control added. FlashChipSetup added, controlled by chip info setupflash struct member. Currently, if enabled, this hangs OLPC in linux PCI scan. chip.h: new struct members added for unwanted device enable, flash setup git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
35befb75ea
commit
da7ee9fa07
9 changed files with 709 additions and 66 deletions
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@ -1,6 +1,7 @@
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struct northbridge_amd_gx2_config
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{
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uint16_t irqmap;
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uint16_t irqmap;
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int setupflash;
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};
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extern struct chip_operations northbridge_amd_gx2_ops;
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@ -163,7 +163,90 @@ pmChipsetInit(void) {
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}
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struct FLASH_DEVICE {
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unsigned char fType; /* Flash type: NOR or NAND */
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unsigned char fInterface; /* Flash interface: I/O or Memory */
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unsigned long fMask; /* Flash size/mask */
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};
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struct FLASH_DEVICE FlashInitTable[] = {
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{ FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K }, /* CS0, or Flash Device 0 */
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{ FLASH_TYPE_NONE, 0, 0 }, /* CS1, or Flash Device 1 */
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{ FLASH_TYPE_NONE, 0, 0 }, /* CS2, or Flash Device 2 */
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{ FLASH_TYPE_NONE, 0, 0 }, /* CS3, or Flash Device 3 */
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};
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#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0]))
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uint32_t FlashPort[] = {
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MDD_LBAR_FLSH0,
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MDD_LBAR_FLSH1,
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MDD_LBAR_FLSH2,
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MDD_LBAR_FLSH3
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};
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/***************************************************************************
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*
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* ChipsetFlashSetup
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*
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* Flash LBARs need to be setup before VSA init so the PCI BARs have
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* correct size info. Call this routine only if flash needs to be
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* configured (don't call it if you want IDE).
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*
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* Entry:
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* Exit:
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* Destroys:
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*
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**************************************************************************/
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static void ChipsetFlashSetup(void)
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{
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msr_t msr;
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int i;
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int numEnabled = 0;
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printk_debug("ChipsetFlashSetup++\n");
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for (i = 0; i < FlashInitTableLen; i++) {
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if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {
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printk_debug("Enable CS%d\n", i);
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/* we need to configure the memory/IO mask */
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msr = rdmsr(FlashPort[i]);
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msr.hi = 0; /* start with the "enabled" bit clear */
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if (FlashInitTable[i].fType == FLASH_TYPE_NAND)
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msr.hi |= 0x00000002;
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else
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msr.hi &= ~0x00000002;
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if (FlashInitTable[i].fInterface == FLASH_IF_MEM)
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msr.hi |= 0x00000004;
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else
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msr.hi &= ~0x00000004;
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msr.hi |= FlashInitTable[i].fMask;
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printk_debug("WRMSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo);
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wrmsr(FlashPort[i], msr);
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/* now write-enable the device */
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msr = rdmsr(MDD_NORF_CNTRL);
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msr.lo |= (1 << i);
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printk_debug("WRMSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo);
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wrmsr(MDD_NORF_CNTRL, msr);
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/* update the number enabled */
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numEnabled++;
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}
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}
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/* enable the flash */
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if (0 != numEnabled) {
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msr = rdmsr(MDD_PIN_OPT);
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msr.lo &= ~1; /* PIN_OPT_IDE */
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printk_debug("WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo);
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wrmsr(MDD_PIN_OPT, msr);
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}
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printk_debug("ChipsetFlashSetup--\n");
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}
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/* ***************************************************************************/
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/* **/
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/* * ChipsetGeodeLinkInit*/
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@ -202,7 +285,7 @@ ChipsetGeodeLinkInit(void){
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}
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void
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chipsetinit (void){
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chipsetinit (struct northbridge_amd_gx2_config *nb){
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msr_t msr;
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struct msrinit *csi;
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int i;
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@ -275,8 +358,9 @@ chipsetinit (void){
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/* Flash Setup*/
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printk_err("NOT DOING ChipsetFlashSetup()!!!!!!!!!!!!!!!!!!\n");
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// ChipsetFlashSetup();
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printk_err("%sDOING ChipsetFlashSetup()!!!!!!!!!!!!!!!!!!\n", nb->setupflash? "NOT " : "");
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if (nb->setupflash)
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ChipsetFlashSetup();
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@ -1,26 +1,32 @@
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#include <arch/io.h>
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#include <stdint.h>
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#include <cpu/amd/vr.h>
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#define VIDEO_MB 8 // MB of video memory
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#define VRC_INDEX 0xAC1C // Index register
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#define VRC_DATA 0xAC1E // Data register
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#define VR_UNLOCK 0xFC53 // Virtual register unlock code
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#define VRC_VG 0x02 // SoftVG Class
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#define VG_MEM_SIZE 0x00 // bits 7:0 - 512K unit size, bit 8 controller priority
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/*
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* Write to a Virtual Register
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* AX = Class/Index
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* CX = data to write
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*/
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static void vrWrite(uint16_t wClassIndex, uint16_t wData)
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void vrWrite(uint16_t wClassIndex, uint16_t wData)
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{
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outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX);
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outw(wData, VRC_DATA);
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}
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/*
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* Read from a Virtual Register
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* AX = Class/Index
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* Returns a 16-bit word of data
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*/
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uint16_t vrRead(uint16_t wClassIndex)
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{
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uint16_t wData;
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outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX);
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wData = inw(VRC_DATA);
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return wData;
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}
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/*
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* This function mirrors the Graphics_Init routine in GeodeROM.
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@ -12,7 +12,7 @@
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#include <cpu/amd/gx2def.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/amd/vr.h>
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#define VIDEO_MB 8
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extern void graphics_init(void);
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@ -120,6 +120,28 @@ struct msr_defaults {
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{0}
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};
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/* note that dev is NOT used -- yet */
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static void irq_init_steering(struct device *dev, uint16_t irq_map) {
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/* Set up IRQ steering */
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uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
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printk_debug("%s(%08X [%08X], %04X)\n", __FUNCTION__, dev, pciAddr, irq_map);
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/* The IRQ steering values (in hex) are effectively dcba, where:
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* <a> represents the IRQ for INTA,
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* <b> represents the IRQ for INTB,
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* <c> represents the IRQ for INTC, and
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* <d> represents the IRQ for INTD.
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* Thus, a value of irq_map = 0xAA5B translates to:
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* INTA = IRQB (IRQ 11)
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* INTB = IRQ5 (IRQ 5)
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* INTC = IRQA (IRQ 10)
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* INTD = IRQA (IRQ 10)
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*/
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outl(pciAddr & ~3, 0xCF8);
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outl(irq_map, 0xCFC);
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}
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/*
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* setup_gx2_cache
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@ -198,11 +220,12 @@ setup_gx2(void)
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msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
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wrmsr(0x40000029, msr);
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#endif
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#if 0
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msr = rdmsr(0x10000028);
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printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
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msr = rdmsr(0x40000029);
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printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
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#endif
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#if 1
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/* fixme: SMM MSR 0x10000026 and 0x400000023 */
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/* calculate the OFFSET field */
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@ -253,9 +276,11 @@ static void enable_shadow(device_t dev)
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static void northbridge_init(device_t dev)
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{
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struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
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printk_debug("northbridge: %s()\n", __FUNCTION__);
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enable_shadow(dev);
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irq_init_steering(dev, nb->irqmap);
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}
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static struct device_operations northbridge_operations = {
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@ -318,6 +343,7 @@ static void tolm_test(void *gp, struct device *dev, struct resource *new)
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*best_p = best;
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}
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#if 0
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static uint32_t find_pci_tolm(struct bus *bus)
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{
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struct resource *min;
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@ -330,7 +356,7 @@ static uint32_t find_pci_tolm(struct bus *bus)
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}
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return tolm;
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}
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#endif
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#define FRAMEBUFFERK 4096
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static void pci_domain_set_resources(device_t dev)
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@ -380,8 +406,8 @@ static void pci_domain_set_resources(device_t dev)
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idx = 10;
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ram_resource(dev, idx++, 0, tolmk);
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}
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assign_resources(&dev->link[0]);
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#endif
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assign_resources(&dev->link[0]);
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}
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static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
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@ -417,33 +443,13 @@ static struct device_operations cpu_bus_ops = {
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void chipsetInit (void);
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/* note that dev is NOT used -- yet */
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static void irq_init(struct device *dev, uint16_t irq_map) {
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/* Set up IRQ steering */
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uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
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printk_debug("OLPC REVA ENTER %s\n", __FUNCTION__);
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/* The IRQ steering values (in hex) are effectively dcba, where:
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* <a> represents the IRQ for INTA,
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* <b> represents the IRQ for INTB,
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* <c> represents the IRQ for INTC, and
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* <d> represents the IRQ for INTD.
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* Thus, a value of irq_map = 0xAA5B translates to:
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* INTA = IRQB (IRQ 11)
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* INTB = IRQ5 (IRQ 5)
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* INTC = IRQA (IRQ 10)
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* INTD = IRQA (IRQ 10)
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*/
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outl(pciAddr & ~3, 0xCF8);
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outl(irq_map, 0xCFC);
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}
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static void enable_dev(struct device *dev)
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{
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printk_debug("gx2 north: enable_dev\n");
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void northbridgeinit(void);
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void chipsetinit(struct northbridge_amd_gx2_config *nb);
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void setup_realmode_idt(void);
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void do_vsmbios(void);
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
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struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
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@ -452,12 +458,11 @@ static void enable_dev(struct device *dev)
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/* cpubug MUST be called before setup_gx2(), so we force the issue here */
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northbridgeinit();
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cpubug();
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chipsetinit();
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chipsetinit(nb);
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setup_gx2();
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/* do this here for now -- this chip really breaks our device model */
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setup_realmode_idt();
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do_vsmbios();
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irq_init(dev, nb->irqmap);
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graphics_init();
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dev->ops = &pci_domain_ops;
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pci_set_method(dev);
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