soc/intel: Add Arrow Lake-S/HX IDs
Change-Id: I7a0a56cf80f053b4bb0c8acb9038c1e46dca5d2e Ref: Intel Arrow Lake-S/HX EDS, Volume 1 (#729037, rev 2.01) Ref: Intel 800 Series Chipset Family PCH EDS, Volume 1 (#728144, rev 1.52) Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87454 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jeremy Soller
Matt DeVillier
parent
8cec500968
commit
da49da6c82
22 changed files with 277 additions and 0 deletions
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@ -2183,6 +2183,7 @@
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#define PCI_DID_INTEL_TGL_H_ISHB 0x43fc
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#define PCI_DID_INTEL_MTL_ISHB 0x7e45
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#define PCI_DID_INTEL_ARL_ISHB 0x7745
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#define PCI_DID_INTEL_ARP_S_ISHB 0x7f78
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#define PCI_DID_INTEL_ADL_N_ISHB 0x54fc
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#define PCI_DID_INTEL_ADL_P_ISHB 0x51fc
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#define PCI_DID_INTEL_LNL_ISHB 0xa845
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@ -3146,6 +3147,70 @@
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#define PCI_DID_INTEL_ARL_H_ESPI_0 0x7202
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#define PCI_DID_INTEL_ARL_H_ESPI_1 0x7702
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#define PCI_DID_INTEL_ARL_U_ESPI_0 0x7203
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#define PCI_DID_INTEL_ARL_S_ESPI_0 0xae00
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#define PCI_DID_INTEL_ARL_S_ESPI_1 0xae01
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#define PCI_DID_INTEL_ARL_S_ESPI_2 0xae02
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#define PCI_DID_INTEL_ARL_S_ESPI_3 0xae03
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#define PCI_DID_INTEL_ARL_S_ESPI_4 0xae04
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#define PCI_DID_INTEL_ARL_S_ESPI_5 0xae05
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#define PCI_DID_INTEL_ARL_S_ESPI_6 0xae06
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#define PCI_DID_INTEL_ARL_S_ESPI_7 0xae07
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#define PCI_DID_INTEL_ARL_S_ESPI_8 0xae08
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#define PCI_DID_INTEL_ARL_S_ESPI_9 0xae09
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#define PCI_DID_INTEL_ARL_S_ESPI_10 0xae0a
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#define PCI_DID_INTEL_ARL_S_ESPI_11 0xae0b
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#define PCI_DID_INTEL_ARL_S_ESPI_12 0xae0c
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#define PCI_DID_INTEL_ARL_S_ESPI_13 0xae0d
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#define PCI_DID_INTEL_ARL_S_ESPI_14 0xae0e
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#define PCI_DID_INTEL_ARL_S_ESPI_15 0xae0f
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#define PCI_DID_INTEL_ARL_S_ESPI_16 0xae10
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#define PCI_DID_INTEL_ARL_S_ESPI_17 0xae11
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#define PCI_DID_INTEL_ARL_S_ESPI_18 0xae12
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#define PCI_DID_INTEL_ARL_S_ESPI_19 0xae13
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#define PCI_DID_INTEL_ARL_S_ESPI_20 0xae14
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#define PCI_DID_INTEL_ARL_S_ESPI_21 0xae15
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#define PCI_DID_INTEL_ARL_S_ESPI_22 0xae16
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#define PCI_DID_INTEL_ARL_S_ESPI_23 0xae17
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#define PCI_DID_INTEL_ARL_S_ESPI_24 0xae18
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#define PCI_DID_INTEL_ARL_S_ESPI_25 0xae19
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#define PCI_DID_INTEL_ARL_S_ESPI_26 0xae1a
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#define PCI_DID_INTEL_ARL_S_ESPI_27 0xae1b
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#define PCI_DID_INTEL_ARL_S_ESPI_28 0xae1c
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#define PCI_DID_INTEL_ARL_S_ESPI_29 0xae1d
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#define PCI_DID_INTEL_ARL_S_ESPI_30 0xae1e
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#define PCI_DID_INTEL_ARL_S_ESPI_31 0xae1f
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#define PCI_DID_INTEL_ARP_S_ESPI_0 0x7f00
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#define PCI_DID_INTEL_ARP_S_ESPI_1 0x7f01
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#define PCI_DID_INTEL_ARP_S_ESPI_2 0x7f02
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#define PCI_DID_INTEL_ARP_S_ESPI_3 0x7f03
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#define PCI_DID_INTEL_ARP_S_ESPI_4 0x7f04
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#define PCI_DID_INTEL_ARP_S_ESPI_5 0x7f05
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#define PCI_DID_INTEL_ARP_S_ESPI_6 0x7f06
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#define PCI_DID_INTEL_ARP_S_ESPI_7 0x7f07
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#define PCI_DID_INTEL_ARP_S_ESPI_8 0x7f08
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#define PCI_DID_INTEL_ARP_S_ESPI_9 0x7f09
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#define PCI_DID_INTEL_ARP_S_ESPI_10 0x7f0a
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#define PCI_DID_INTEL_ARP_S_ESPI_11 0x7f0b
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#define PCI_DID_INTEL_ARP_S_ESPI_12 0x7f0c
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#define PCI_DID_INTEL_ARP_S_ESPI_13 0x7f0d
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#define PCI_DID_INTEL_ARP_S_ESPI_14 0x7f0e
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#define PCI_DID_INTEL_ARP_S_ESPI_15 0x7f0f
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#define PCI_DID_INTEL_ARP_S_ESPI_16 0x7f10
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#define PCI_DID_INTEL_ARP_S_ESPI_17 0x7f11
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#define PCI_DID_INTEL_ARP_S_ESPI_18 0x7f12
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#define PCI_DID_INTEL_ARP_S_ESPI_19 0x7f13
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#define PCI_DID_INTEL_ARP_S_ESPI_20 0x7f14
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#define PCI_DID_INTEL_ARP_S_ESPI_21 0x7f15
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#define PCI_DID_INTEL_ARP_S_ESPI_22 0x7f16
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#define PCI_DID_INTEL_ARP_S_ESPI_23 0x7f17
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#define PCI_DID_INTEL_ARP_S_ESPI_24 0x7f18
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#define PCI_DID_INTEL_ARP_S_ESPI_25 0x7f19
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#define PCI_DID_INTEL_ARP_S_ESPI_26 0x7f1a
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#define PCI_DID_INTEL_ARP_S_ESPI_27 0x7f1b
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#define PCI_DID_INTEL_ARP_S_ESPI_28 0x7f1c
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#define PCI_DID_INTEL_ARP_S_ESPI_29 0x7f1d
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#define PCI_DID_INTEL_ARP_S_ESPI_30 0x7f1e
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#define PCI_DID_INTEL_ARP_S_ESPI_31 0x7f1f
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#define PCI_DID_INTEL_RPP_P_ESPI_0 0x5180
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#define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1 0x5181
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#define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2 0x5182
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@ -3650,6 +3715,34 @@
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#define PCI_DID_INTEL_ARL_SOC_PCIE_RP7 0x773e
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#define PCI_DID_INTEL_ARL_SOC_PCIE_RP8 0x773f
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#define PCI_DID_INTEL_ARL_SOC_PCIE_RP9 0x774d
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#define PCI_DID_INTEL_ARL_S_PCIE_RP13 0xae4d
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#define PCI_DID_INTEL_ARL_S_PCIE_RP14 0xae4e
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#define PCI_DID_INTEL_ARL_S_PCIE_RP15 0xae4f
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#define PCI_DID_INTEL_ARP_S_PCIE_RP1 0x7f38
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#define PCI_DID_INTEL_ARP_S_PCIE_RP2 0x7f39
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#define PCI_DID_INTEL_ARP_S_PCIE_RP3 0x7f3a
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#define PCI_DID_INTEL_ARP_S_PCIE_RP4 0x7f3b
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#define PCI_DID_INTEL_ARP_S_PCIE_RP5 0x7f3c
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#define PCI_DID_INTEL_ARP_S_PCIE_RP6 0x7f3d
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#define PCI_DID_INTEL_ARP_S_PCIE_RP7 0x7f3e
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#define PCI_DID_INTEL_ARP_S_PCIE_RP8 0x7f3f
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#define PCI_DID_INTEL_ARP_S_PCIE_RP9 0x7f30
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#define PCI_DID_INTEL_ARP_S_PCIE_RP10 0x7f31
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#define PCI_DID_INTEL_ARP_S_PCIE_RP11 0x7f32
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#define PCI_DID_INTEL_ARP_S_PCIE_RP12 0x7f33
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#define PCI_DID_INTEL_ARP_S_PCIE_RP13 0x7f34
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#define PCI_DID_INTEL_ARP_S_PCIE_RP14 0x7f35
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#define PCI_DID_INTEL_ARP_S_PCIE_RP15 0x7f36
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#define PCI_DID_INTEL_ARP_S_PCIE_RP16 0x7f37
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#define PCI_DID_INTEL_ARP_S_PCIE_RP17 0x7f40
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#define PCI_DID_INTEL_ARP_S_PCIE_RP18 0x7f41
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#define PCI_DID_INTEL_ARP_S_PCIE_RP19 0x7f42
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#define PCI_DID_INTEL_ARP_S_PCIE_RP20 0x7f43
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#define PCI_DID_INTEL_ARP_S_PCIE_RP21 0x7f44
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#define PCI_DID_INTEL_ARP_S_PCIE_RP22 0x7f45
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#define PCI_DID_INTEL_ARP_S_PCIE_RP23 0x7f46
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#define PCI_DID_INTEL_ARP_S_PCIE_RP24 0x7f47
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#define PCI_DID_INTEL_RPL_P_PCIE_RP1 0xa74d
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#define PCI_DID_INTEL_RPL_P_PCIE_RP2 0xa70d
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@ -3820,6 +3913,8 @@
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#define PCI_DID_INTEL_ADP_M_SATA_3 0x282a
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#define PCI_DID_INTEL_MTL_SATA 0x7e63
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#define PCI_DID_INTEL_ARL_SATA 0x7763
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#define PCI_DID_INTEL_ARP_S_SATA_1 0x7f62
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#define PCI_DID_INTEL_ARP_S_SATA_2 0x7f66
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#define PCI_DID_INTEL_RPP_P_SATA_1 0x51d3
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#define PCI_DID_INTEL_RPP_P_SATA_2 0x51d7
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#define PCI_DID_INTEL_RPP_S_SATA 0x7a62
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@ -3850,6 +3945,8 @@
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#define PCI_DID_INTEL_MTL_IOE_M_PMC 0x7ebe
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#define PCI_DID_INTEL_MTL_IOE_P_PMC 0x7ece
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#define PCI_DID_INTEL_ARL_SOC_PMC 0x7721
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#define PCI_DID_INTEL_ARL_IOE_S_PMC 0xae21
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#define PCI_DID_INTEL_ARP_S_PMC 0x7f21
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#define PCI_DID_INTEL_RPP_P_PMC 0x51a1
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#define PCI_DID_INTEL_RPP_S_PMC 0x7a21
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#define PCI_DID_INTEL_LNL_PMC 0xa821
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@ -3987,6 +4084,13 @@
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#define PCI_DID_INTEL_ARL_I2C4 0x7750
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#define PCI_DID_INTEL_ARL_I2C5 0x7751
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#define PCI_DID_INTEL_ARP_S_I2C0 0x7f4c
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#define PCI_DID_INTEL_ARP_S_I2C1 0x7f4d
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#define PCI_DID_INTEL_ARP_S_I2C2 0x7f4e
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#define PCI_DID_INTEL_ARP_S_I2C3 0x7f4f
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#define PCI_DID_INTEL_ARP_S_I2C4 0x7f7a
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#define PCI_DID_INTEL_ARP_S_I2C5 0x7f7b
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#define PCI_DID_INTEL_LNL_I2C0 0xa878
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#define PCI_DID_INTEL_LNL_I2C1 0xa879
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#define PCI_DID_INTEL_LNL_I2C2 0xa87a
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@ -4097,6 +4201,11 @@
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#define PCI_DID_INTEL_ARL_UART1 0x7726
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#define PCI_DID_INTEL_ARL_UART2 0x7752
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#define PCI_DID_INTEL_ARP_S_UART0 0x7f28
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#define PCI_DID_INTEL_ARP_S_UART1 0x7f29
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#define PCI_DID_INTEL_ARP_S_UART2 0x7f5c
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#define PCI_DID_INTEL_ARP_S_UART3 0x7f5d
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#define PCI_DID_INTEL_LNL_UART0 0xa825
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#define PCI_DID_INTEL_LNL_UART1 0xa826
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#define PCI_DID_INTEL_LNL_UART2 0xa852
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@ -4211,6 +4320,13 @@
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#define PCI_DID_INTEL_ARL_GSPI1 0x7730
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#define PCI_DID_INTEL_ARL_GSPI2 0x7746
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#define PCI_DID_INTEL_ARL_S_HWSEQ_SPI 0xae23
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#define PCI_DID_INTEL_ARP_S_HWSEQ_SPI 0x7f24
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#define PCI_DID_INTEL_ARP_S_GSPI0 0x7f2a
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#define PCI_DID_INTEL_ARP_S_GSPI1 0x7f2b
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#define PCI_DID_INTEL_ARP_S_GSPI2 0x7f5e
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#define PCI_DID_INTEL_ARP_S_GSPI3 0x7f5f
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#define PCI_DID_INTEL_LNL_HWSEQ_SPI 0xa823
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#define PCI_DID_INTEL_LNL_GSPI0 0xa827
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#define PCI_DID_INTEL_LNL_GSPI1 0xa830
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#define PCI_DID_INTEL_ADP_M_N_SMBUS 0x54a3
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#define PCI_DID_INTEL_MTL_SMBUS 0x7e22
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#define PCI_DID_INTEL_ARL_SMBUS 0x7722
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#define PCI_DID_INTEL_ARL_S_SMBUS 0xae22
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#define PCI_DID_INTEL_ARP_S_SMBUS 0x7f22
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#define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3
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#define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23
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#define PCI_DID_INTEL_LNL_SMBUS 0xa822
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#define PCI_DID_INTEL_MTL_M_TCSS_XHCI 0x7eb0
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#define PCI_DID_INTEL_MTL_P_TCSS_XHCI 0x7ec0
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#define PCI_DID_INTEL_ARL_XHCI 0x777d
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#define PCI_DID_INTEL_ARP_S_XHCI 0x7f6e
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#define PCI_DID_INTEL_RPP_P_TCSS_XHCI 0xa71e
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#define PCI_DID_INTEL_RPP_S_XHCI 0x7a60
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#define PCI_DID_INTEL_LNL_XHCI 0xa87d
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#define PCI_DID_INTEL_MTL_IOE_M_P2SB 0x7eb8
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#define PCI_DID_INTEL_MTL_IOE_P_P2SB 0x7ec8
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#define PCI_DID_INTEL_ARL_SOC_P2SB 0x7720
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#define PCI_DID_INTEL_ARL_IOE_S_P2SB 0xae20
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#define PCI_DID_INTEL_ARP_S_P2SB 0x7f20
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#define PCI_DID_INTEL_RPP_P_P2SB 0x51a0
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#define PCI_DID_INTEL_RPP_S_P2SB 0x7a20
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#define PCI_DID_INTEL_LNL_P2SB 0xa820
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#define PCI_DID_INTEL_MTL_IOE_M_SRAM 0x7ebf
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#define PCI_DID_INTEL_MTL_IOE_P_SRAM 0x7ecf
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#define PCI_DID_INTEL_ARL_SOC_SRAM 0x777f
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#define PCI_DID_INTEL_ARL_SOC_S_SRAM 0xae7f
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#define PCI_DID_INTEL_ARP_S_SRAM 0x7f27
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#define PCI_DID_INTEL_LNL_SRAM 0xa87f
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#define PCI_DID_INTEL_PTL_H_SRAM 0xe47f
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#define PCI_DID_INTEL_PTL_U_H_SRAM 0xe37f
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#define PCI_DID_INTEL_ARL_AUDIO 0x7728
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#define PCI_DID_INTEL_ARP_S_AUDIO 0x7f50
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#define PCI_DID_INTEL_LNL_AUDIO_1 0xa828
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#define PCI_DID_INTEL_LNL_AUDIO_2 0xa829
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#define PCI_DID_INTEL_LNL_AUDIO_3 0xa82a
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#define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d
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#define PCI_DID_INTEL_MTL_CSE0 0x7e70
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#define PCI_DID_INTEL_ARL_CSE0 0x7770
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#define PCI_DID_INTEL_ARL_S_CSE0 0xae70
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#define PCI_DID_INTEL_ARL_S_CSE1 0xae71
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#define PCI_DID_INTEL_ARL_S_CSE2 0xae74
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#define PCI_DID_INTEL_ARP_S_CSE0 0x7f68
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#define PCI_DID_INTEL_ARP_S_CSE1 0x7f69
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#define PCI_DID_INTEL_ARP_S_CSE2 0x7f6c
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#define PCI_DID_INTEL_ARP_S_CSE3 0x7f6d
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#define PCI_DID_INTEL_LNL_CSE0 0xa870
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#define PCI_DID_INTEL_PTL_H_CSE0 0xe470
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#define PCI_DID_INTEL_PTL_U_H_CSE0 0xe370
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#define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1
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#define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1
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#define PCI_DID_INTEL_ARL_XDCI 0x777e
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#define PCI_DID_INTEL_ARP_S_XDCI 0x7f6f
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#define PCI_DID_INTEL_PTL_H_XDCI 0xe47e
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#define PCI_DID_INTEL_PTL_U_H_XDCI 0xe37e
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#define PCI_DID_INTEL_WCL_XDCI 0x4d7e
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#define PCI_DID_INTEL_JSL_DTT 0x4E03
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#define PCI_DID_INTEL_ADL_DTT 0x461d
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#define PCI_DID_INTEL_MTL_DTT 0x7d03
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#define PCI_DID_INTEL_ARL_S_DTT 0xad03
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#define PCI_DID_INTEL_RPL_DTT 0xa71d
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#define PCI_DID_INTEL_PTL_DTT 0xb01d
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#define PCI_DID_INTEL_WCL_DTT 0xfd1d
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#define PCI_DID_INTEL_MTL_CNVI_WIFI_2 0x7e42
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#define PCI_DID_INTEL_MTL_CNVI_WIFI_3 0x7e43
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#define PCI_DID_INTEL_ARL_CNVI_WIFI 0x7740
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#define PCI_DID_INTEL_ARP_S_CNVI_WIFI 0x7f70
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#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_0 0x7a70
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#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1 0x7a71
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#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2 0x7a72
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#define PCI_DID_INTEL_ADP_N_PMC_CRASHLOG_SRAM 0x54ef
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#define PCI_DID_INTEL_TGP_PMC_CRASHLOG_SRAM 0xa0ef
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#define PCI_DID_INTEL_MTL_CRASHLOG_SRAM 0x7d0d
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#define PCI_DID_INTEL_ARL_S_CRASHLOG_SRAM 0xad0d
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#define PCI_DID_INTEL_RPL_CPU_CRASHLOG_SRAM 0xa77d
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#define PCI_DID_INTEL_RPP_S_PMC_CRASHLOG_SRAM 0x7a27
|
||||
#define PCI_DID_INTEL_PTL_PUNIT_CRASHLOG_SRAM 0xb07d
|
||||
|
|
@ -5087,6 +5223,8 @@
|
|||
/* Intel Trace Hub */
|
||||
#define PCI_DID_INTEL_MTL_TRACEHUB 0x7e24
|
||||
#define PCI_DID_INTEL_ARL_TRACEHUB 0x7724
|
||||
#define PCI_DID_INTEL_ARL_S_TRACEHUB 0xae24
|
||||
#define PCI_DID_INTEL_ARP_S_TRACEHUB 0x7f26
|
||||
#define PCI_DID_INTEL_RPL_TRACEHUB 0xa76f
|
||||
#define PCI_DID_INTEL_PTL_H_TRACEHUB 0xe424
|
||||
#define PCI_DID_INTEL_PTL_U_H_TRACEHUB 0xe324
|
||||
|
|
@ -5118,6 +5256,10 @@
|
|||
#define PCI_DID_INTEL_ARL_THC0_2 0x7749
|
||||
#define PCI_DID_INTEL_ARL_THC1_1 0x774a
|
||||
#define PCI_DID_INTEL_ARL_THC1_2 0x774b
|
||||
#define PCI_DID_INTEL_ARP_S_THC0_1 0x7f58
|
||||
#define PCI_DID_INTEL_ARP_S_THC0_2 0x7f59
|
||||
#define PCI_DID_INTEL_ARP_S_THC1_1 0x7f5a
|
||||
#define PCI_DID_INTEL_ARP_S_THC1_2 0x7f5b
|
||||
|
||||
#define PCI_VID_COMPUTONE 0x8e0e
|
||||
#define PCI_DID_COMPUTONE_IP2EX 0x0291
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue