From da122fe8f523bf85dedc9799b9aebe1a2d2b64e6 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Wed, 11 Jun 2025 11:48:58 +0100 Subject: [PATCH] mb/starlabs/*: Use PLTRST for PCH Strap GPIOs Replace RSMRST with PLTRST, for the PCH Strap GPIOs. RSMRST introduced programming errors in cbmem (gpio_pad_reset_config_override: logical to chipset mapping not found) and broke tablet mode rotation. Change-Id: Ia2b655450558a9de98ce1a92c93820ab3da57ca0 Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/88053 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- .../starlabs/byte_adl/variants/mk_ii/gpio.c | 24 ++++++++--------- .../starlabs/starbook/variants/adl_n/gpio.c | 26 +++++++++---------- .../starlabs/starbook/variants/mtl/gpio.c | 18 ++++++------- .../starlabs/starbook/variants/tgl/gpio.c | 24 ++++++++--------- .../starlabs/starfighter/variants/rpl/gpio.c | 18 ++++++------- .../starlite_adl/variants/mk_v/gpio.c | 24 ++++++++--------- 6 files changed, 67 insertions(+), 67 deletions(-) diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c index b6aa4dbdbc..01a4d5dcd0 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c @@ -84,18 +84,18 @@ const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_E8, 1, DEEP), /* DRAM Sleep */ /* Config Straps [ Low / High ] */ - PAD_CFG_GPO(GPP_B14, 0, RSMRST), /* Top Swap [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_B18, 0, RSMRST), /* Reboot Support [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_C2, 1, RSMRST), /* TLS Confidentiality [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_C5, 0, RSMRST), /* eSPI [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_E6, 0, RSMRST), /* JTAG ODT [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_H1, 0, RSMRST), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_E19, 0, RSMRST), /* TBT LSX #0 [ 1.8V / 3.3V ] */ - PAD_CFG_GPO(GPP_E21, 0, RSMRST), /* TBT LSX #1 [ 1.8V / 3.3V ] */ - PAD_CFG_GPO(GPP_D10, 0, RSMRST), /* TBT LSX #2 [ 1.8V / 3.3V ] */ - PAD_CFG_GPO(GPP_D12, 0, RSMRST), /* TBT LSX #3 [ 1.8V / 3.3V ] */ - PAD_CFG_GPO(GPP_F7, 0, RSMRST), /* MCRO LDO [ Disabled / Bypass ] */ - PAD_CFG_GPO(GPD7, 0, RSMRST), /* RTC Clock Delay [ Disabled / 95ms ] */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* Top Swap [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* Reboot Support [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* TLS Confidentiality [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_C5, 0, PLTRST), /* eSPI [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_E6, 0, PLTRST), /* JTAG ODT [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_H1, 0, PLTRST), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_E19, 0, PLTRST), /* TBT LSX #0 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_E21, 0, PLTRST), /* TBT LSX #1 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_D10, 0, PLTRST), /* TBT LSX #2 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_D12, 0, PLTRST), /* TBT LSX #3 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_F7, 0, PLTRST), /* MCRO LDO [ Disabled / Bypass ] */ + PAD_CFG_GPO(GPD7, 0, PLTRST), /* RTC Clock Delay [ Disabled / 95ms ] */ PAD_NC(GPD2, NONE), PAD_NC(GPD6, NONE), diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c index 1e4899b59a..fb82f3edf3 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c @@ -80,19 +80,19 @@ const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_E8, 1, DEEP), /* DRAM Sleep */ /* Config Straps [ Low / High ] */ - PAD_CFG_GPO(GPP_B14, 0, RSMRST), /* Top Swap [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_B18, 0, RSMRST), /* Reboot Support [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_C2, 1, RSMRST), /* TLS Confidentiality [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_C5, 0, RSMRST), /* eSPI [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_E6, 0, RSMRST), /* JTAG ODT [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_H1, 0, RSMRST), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_F2, 1, RSMRST), /* M.2 CNVi [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_E19, 0, RSMRST), /* TBT LSX #0 [ 1.8V / 3.3V ] */ - PAD_CFG_GPO(GPP_E21, 0, RSMRST), /* TBT LSX #1 [ 1.8V / 3.3V ] */ - PAD_CFG_GPO(GPP_D10, 0, RSMRST), /* TBT LSX #2 [ 1.8V / 3.3V ] */ - PAD_CFG_GPO(GPP_D12, 0, RSMRST), /* TBT LSX #3 [ 1.8V / 3.3V ] */ - PAD_CFG_GPO(GPP_F7, 0, RSMRST), /* MCRO LDO [ Disabled / Bypass ] */ - PAD_CFG_GPO(GPD7, 0, RSMRST), /* RTC Clock Delay [ Disabled / 95ms ] */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* Top Swap [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* Reboot Support [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* TLS Confidentiality [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_C5, 0, PLTRST), /* eSPI [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_E6, 0, PLTRST), /* JTAG ODT [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_H1, 0, PLTRST), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_F2, 1, PLTRST), /* M.2 CNVi [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_E19, 0, PLTRST), /* TBT LSX #0 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_E21, 0, PLTRST), /* TBT LSX #1 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_D10, 0, PLTRST), /* TBT LSX #2 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_D12, 0, PLTRST), /* TBT LSX #3 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_F7, 0, PLTRST), /* MCRO LDO [ Disabled / Bypass ] */ + PAD_CFG_GPO(GPD7, 0, PLTRST), /* RTC Clock Delay [ Disabled / 95ms ] */ PAD_NC(GPD2, NONE), PAD_NC(GPD6, NONE), diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c index 618df01b19..435840cf8e 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c @@ -79,15 +79,15 @@ const struct pad_config gpio_table[] = { PAD_CFG_GPI_APIC_LOW(GPP_F13, NONE, PLTRST), /* Interrupt */ /* Config Straps [ Low / High ] */ - PAD_CFG_GPO(GPP_B14, 0, RSMRST), /* Top Swap [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_B04, 0, RSMRST), /* Reboot Support [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_C02, 1, RSMRST), /* TLS Confidentiality [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_C05, 0, RSMRST), /* eSPI [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_E06, 0, RSMRST), /* JTAG ODT [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_F02, 0, RSMRST), /* M.2 CNVi [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_H01, 0, RSMRST), /* Flash Recovery [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_F20, 0, RSMRST), /* SVID [ Present / Disabled ] */ - PAD_CFG_GPO(GPP_F21, 0, RSMRST), /* CCD [ BSSB-LS / BALTIC ] */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* Top Swap [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_B04, 0, PLTRST), /* Reboot Support [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_C02, 1, PLTRST), /* TLS Confidentiality [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_C05, 0, PLTRST), /* eSPI [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_E06, 0, PLTRST), /* JTAG ODT [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_F02, 0, PLTRST), /* M.2 CNVi [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_H01, 0, PLTRST), /* Flash Recovery [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_F20, 0, PLTRST), /* SVID [ Present / Disabled ] */ + PAD_CFG_GPO(GPP_F21, 0, PLTRST), /* CCD [ BSSB-LS / BALTIC ] */ PAD_NC(GPP_V02, NONE), PAD_NC(GPP_V06, NONE), diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c index 0bb71f4130..f36b9a3ba3 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c @@ -94,18 +94,18 @@ const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* Data */ /* Config Straps [ Low / High ] */ - PAD_CFG_GPO(GPP_B14, 0, RSMRST), /* Top Swap [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_B18, 0, RSMRST), /* Reboot Support [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_C2, 1, RSMRST), /* TLS Confidentiality [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_B22, 0, RSMRST), /* eSPI [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_E6, 0, RSMRST), /* JTAG ODT [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_C5, 0, RSMRST), /* BFX Strap 2 Bit 1 [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_H0, 0, RSMRST), /* BFX Strap 2 Bit 2 [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_H1, 0, RSMRST), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_H2, 0, RSMRST), /* BFX Strap 2 Bit 4 [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_E21, 0, RSMRST), /* TBT LSX #1 [ 1,8V / 3.3V ] */ - PAD_CFG_GPO(GPP_F7, 0, RSMRST), /* MCRO LDO [ Disabled / Bypass ] */ - PAD_CFG_GPO(GPD7, 0, RSMRST), /* RTC Clock Delay [ Disabled / 95ms ] */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* Top Swap [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* Reboot Support [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* TLS Confidentiality [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_B22, 0, PLTRST), /* eSPI [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_E6, 0, PLTRST), /* JTAG ODT [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_C5, 0, PLTRST), /* BFX Strap 2 Bit 1 [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_H0, 0, PLTRST), /* BFX Strap 2 Bit 2 [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_H1, 0, PLTRST), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_H2, 0, PLTRST), /* BFX Strap 2 Bit 4 [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_E21, 0, PLTRST), /* TBT LSX #1 [ 1,8V / 3.3V ] */ + PAD_CFG_GPO(GPP_F7, 0, PLTRST), /* MCRO LDO [ Disabled / Bypass ] */ + PAD_CFG_GPO(GPD7, 0, PLTRST), /* RTC Clock Delay [ Disabled / 95ms ] */ PAD_CFG_GPO(GPP_B23, 0, DEEP), /* CPUNSSC [ 19.2MHz / 38.4MHz ] */ PAD_CFG_GPO(GPP_F10, 0, DEEP), /* XTAL Mode [ Attached / Single ] */ diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c index 82872e8413..0195ac9033 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c +++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c @@ -100,15 +100,15 @@ const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_E8, 1, DEEP), /* DRAM Sleep */ /* Config Straps [ Low / High ] */ - PAD_CFG_GPO(GPP_B14, 0, RSMRST), /* Top Swap [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_B18, 0, RSMRST), /* Reboot Support [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_C2, 1, RSMRST), /* TLS Confidentiality [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_C5, 0, RSMRST), /* eSPI [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_E6, 0, RSMRST), /* JTAG ODT [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_H1, 0, RSMRST), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_F2, 1, RSMRST), /* M.2 CNVi [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_F7, 0, RSMRST), /* MCRO LDO [ Disabled / Bypass ] */ - PAD_CFG_GPO(GPD7, 0, RSMRST), /* RTC Clock Delay [ Disabled / 95ms ] */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* Top Swap [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* Reboot Support [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* TLS Confidentiality [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_C5, 0, PLTRST), /* eSPI [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_E6, 0, PLTRST), /* JTAG ODT [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_H1, 0, PLTRST), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_F2, 1, PLTRST), /* M.2 CNVi [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_F7, 0, PLTRST), /* MCRO LDO [ Disabled / Bypass ] */ + PAD_CFG_GPO(GPD7, 0, PLTRST), /* RTC Clock Delay [ Disabled / 95ms ] */ PAD_NC(GPD2, NONE), PAD_NC(GPD6, NONE), diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c index 09cd782f54..9cf3a3e2bd 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c @@ -91,18 +91,18 @@ const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_E8, 1, DEEP), /* DRAM Sleep */ /* Config Straps [ Low / High ] */ - PAD_CFG_GPO(GPP_B14, 0, RSMRST), /* Top Swap [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_B18, 0, RSMRST), /* Reboot Support [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_C2, 1, RSMRST), /* TLS Confidentiality [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_C5, 0, RSMRST), /* eSPI [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_E6, 0, RSMRST), /* JTAG ODT [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_H1, 0, RSMRST), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_E19, 0, RSMRST), /* TBT LSX #0 [ 1.8V / 3.3V ] */ - PAD_CFG_GPO(GPP_E21, 0, RSMRST), /* TBT LSX #1 [ 1.8V / 3.3V ] */ - PAD_CFG_GPO(GPP_D10, 0, RSMRST), /* TBT LSX #2 [ 1.8V / 3.3V ] */ - PAD_CFG_GPO(GPP_D12, 0, RSMRST), /* TBT LSX #3 [ 1.8V / 3.3V ] */ - PAD_CFG_GPO(GPP_F7, 0, RSMRST), /* MCRO LDO [ Disabled / Bypass ] */ - PAD_CFG_GPO(GPD7, 0, RSMRST), /* RTC Clock Delay [ Disabled / 95ms ] */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* Top Swap [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* Reboot Support [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* TLS Confidentiality [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_C5, 0, PLTRST), /* eSPI [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_E6, 0, PLTRST), /* JTAG ODT [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_H1, 0, PLTRST), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_E19, 0, PLTRST), /* TBT LSX #0 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_E21, 0, PLTRST), /* TBT LSX #1 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_D10, 0, PLTRST), /* TBT LSX #2 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_D12, 0, PLTRST), /* TBT LSX #3 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_F7, 0, PLTRST), /* MCRO LDO [ Disabled / Bypass ] */ + PAD_CFG_GPO(GPD7, 0, PLTRST), /* RTC Clock Delay [ Disabled / 95ms ] */ PAD_NC(GPD2, NONE), PAD_NC(GPD6, NONE),