From da016515f672f1f2e2cbfe8ff81a168fdf4ea647 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 19 Jul 2016 17:39:05 -0500 Subject: [PATCH] UPSTREAM: mainboard/google/reef: reverse the memory config bits I mistakenly assumed the order of the bits matched how one would assign values as they wrote them msb .. lsb. However, the gpio lib doesn't do that. Correct the order so that values are read out correctly. BUG=chrome-os-partner:54949t BRANCH=None TEST=None Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/15753 Reviewed-by: Duncan Laurie Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Change-Id: I5304dfe2ba6f8eb073acab3377327167573ec2cc Reviewed-on: https://chromium-review.googlesource.com/362344 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Furquan Shaikh --- src/mainboard/google/reef/romstage.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index 2c68b60d46..8b7c7a3f58 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -112,7 +112,10 @@ static const struct lpddr4_cfg lp4cfg = { void mainboard_memory_init_params(struct FSPM_UPD *memupd) { int mem_sku; - gpio_t pads[] = { MEM_CONFIG3, MEM_CONFIG2, MEM_CONFIG1, MEM_CONFIG0 }; + gpio_t pads[] = { + [3] = MEM_CONFIG3, [2] = MEM_CONFIG2, + [1] = MEM_CONFIG1, [0] = MEM_CONFIG0, + }; /* * Read memory SKU id with internal pullups enabled to handle