From d9e50b1343600398c8922e44de08e394daed3dcf Mon Sep 17 00:00:00 2001 From: Zhuohao Lee Date: Tue, 18 Jan 2022 23:56:16 +0800 Subject: [PATCH] util/mb/google: add support for brask Add the file templates for creating a new variant of Brask. BUG=b:215091592 TEST=new_variant.py and build coreboot pass for the new variant. Change-Id: I67e4ed450d6033fed7419bd7c76c127ecd942fe8 Signed-off-by: Zhuohao Lee Reviewed-on: https://review.coreboot.org/c/coreboot/+/61184 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- util/mainboard/google/brask/template/include/variant/ec.h | 8 ++++++++ .../google/brask/template/include/variant/gpio.h | 8 ++++++++ util/mainboard/google/brask/template/overridetree.cb | 6 ++++++ 3 files changed, 22 insertions(+) create mode 100644 util/mainboard/google/brask/template/include/variant/ec.h create mode 100644 util/mainboard/google/brask/template/include/variant/gpio.h create mode 100644 util/mainboard/google/brask/template/overridetree.cb diff --git a/util/mainboard/google/brask/template/include/variant/ec.h b/util/mainboard/google/brask/template/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/util/mainboard/google/brask/template/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/util/mainboard/google/brask/template/include/variant/gpio.h b/util/mainboard/google/brask/template/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/util/mainboard/google/brask/template/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/util/mainboard/google/brask/template/overridetree.cb b/util/mainboard/google/brask/template/overridetree.cb new file mode 100644 index 0000000000..4f2c04a57a --- /dev/null +++ b/util/mainboard/google/brask/template/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end