diff --git a/src/mainboard/siemens/mc_rpl/mainboard.c b/src/mainboard/siemens/mc_rpl/mainboard.c
index a96ab859cd..69670aa0ec 100644
--- a/src/mainboard/siemens/mc_rpl/mainboard.c
+++ b/src/mainboard/siemens/mc_rpl/mainboard.c
@@ -2,18 +2,18 @@
 
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
+#include <cpu/x86/msr.h>
 #include <device/device.h>
-#include <soc/gpio.h>
-#include <stdint.h>
-#include <stdio.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
 #include <hwilib.h>
 #include <i210.h>
-#include <soc/ramstage.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <cpu/x86/msr.h>
+#include <soc/gpio.h>
 #include <soc/msr.h>
+#include <soc/ramstage.h>
+#include <stdint.h>
+#include <stdio.h>
 
 #define MAX_PATH_DEPTH		12
 #define MAX_NUM_MAPPINGS	10
diff --git a/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c b/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c
index 0026821820..5310746832 100644
--- a/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c
+++ b/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c
@@ -1,12 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <baseboard/variants.h>
 #include <console/console.h>
 #include <fsp/api.h>
 #include <hwilib.h>
+#include <soc/meminit.h>
 #include <soc/romstage.h>
 #include <spd_bin.h>
-#include <soc/meminit.h>
-#include <baseboard/variants.h>
 
 /*
  * ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/variant.c b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/variant.c
index 91f5cbd496..86e1ddf2eb 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/variant.c
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/variant.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <baseboard/variants.h>
 #include <console/console.h>
 #include <fsp/api.h>
-#include <baseboard/variants.h>
 
 void variant_configure_fspm(FSPM_UPD *memupd)
 {