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UPSTREAM: intel PCI ops: Remove explicit PCI MMCONF access

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MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
being non-atomic and/or need to access 4kiB of PCI config space.

All these platforms now have MMCONF_SUPPORT_DEFAULT.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17529
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11
Reviewed-on: https://chromium-review.googlesource.com/417077
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2013-07-26 08:53:59 +03:00 • committed by chrome-bot
commit d95ea59eff
17 changed files with 146 additions and 146 deletions
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6
src/soc/intel/sch/smihandler.c
View file

@ -275,7 +275,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
u16 pm1_sts;
u32 smi_sts, gpe0_sts, tco_sts;
pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x48) & 0xfffc;
pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x48) & 0xfffc;
printk(BIOS_SPEW, "SMI#: pmbase = 0x%04x\n", pmbase);
/* We need to clear the SMI status registers, or we won't see what's
@ -325,7 +325,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
if (tco_sts & (1 << 8)) { // BIOSWR
u8 bios_cntl;
bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
if (bios_cntl & 1) {
/* BWE is RW, so the SMI was caused by a
* write to BWE, not by a write to the BIOS
@ -338,7 +338,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
* box.
*/
printk(BIOS_DEBUG, "Switching back to RO\n");
pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
} /* No else for now? */
}
}