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riscv: Add support for timer interrupts

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RISCV requires that timer interrupts be handled in machine
mode and delegated as necessary. Also you can only reset the
timer interrupt by writing to mtimecmp. Further, you must
write a number > mtime, not just != mtime. This rather clumsy
situation requires that we write some value into the future
into mtimecmp lest we never be able to leave machine mode as
the interrupt either is not cleared or instantly reoccurs.

This current code is tested and works for harvey (Plan 9)
timer interrupts.

Change-Id: I8538d5fd8d80d9347773c638f5cbf0da18dc1cae
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17807
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
This commit is contained in:
Ronald G. Minnich 2016-12-12 15:09:42 -08:00
commit d9307c2e8a
3 changed files with 94 additions and 4 deletions
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6
src/arch/riscv/include/arch/encoding.h
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@ -48,6 +48,11 @@
#define MSTATUS32_SD 0x80000000
#define MSTATUS64_SD 0x8000000000000000
#define MIE_UTIE 0x00000010
#define MIE_STIE 0x00000020
#define MIE_HTIE 0x00000040
#define MIE_MTIE 0x00000080
#define SSTATUS_UIE 0x00000001
#define SSTATUS_SIE 0x00000002
#define SSTATUS_UPIE 0x00000010
@ -126,6 +131,7 @@
#define SIP_SSIP MIP_SSIP
#define SIP_STIP MIP_STIP
#define SIE_STIE MIE_STIE
#define PRV_U 0
#define PRV_S 1