diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk index eb1ce41b48..4f74401cbc 100644 --- a/src/soc/mediatek/mt8189/Makefile.mk +++ b/src/soc/mediatek/mt8189/Makefile.mk @@ -35,6 +35,9 @@ romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c ramstage-y += ../common/auxadc.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c ramstage-y += ../common/dpm.c ../common/dpm_v2.c +ramstage-y += ../common/dp/dp_intf_v2.c +ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_v2.c dptx.c +ramstage-y += ../common/dp/dptx_hal_common.c ../common/dp/dptx_hal_v2.c dptx_hal.c ramstage-y += ../common/dramc_info.c ramstage-y += ../common/emi.c ramstage-y += ../common/mcu.c mcupm.c @@ -58,6 +61,7 @@ BL31_MAKEARGS += PLAT=mt8189 CPPFLAGS_common += -Isrc/soc/mediatek/mt8189/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include +CPPFLAGS_common += -Isrc/soc/mediatek/common/dp/include MT8189_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8189 diff --git a/src/soc/mediatek/mt8189/dptx.c b/src/soc/mediatek/mt8189/dptx.c new file mode 100644 index 0000000000..c07195ff06 --- /dev/null +++ b/src/soc/mediatek/mt8189/dptx.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 10.28 + */ + +#include +#include +#include +#include + +void dptx_set_tx_power_con(void) +{ +} + +void dptx_set_26mhz_clock(void) +{ + write32p(CKSYS_BASE + CKSYS_CLK_CFG_16_CLR, 0xFF000000); + write32p(CKSYS_BASE + CKSYS_CLK_CFG_UPDATE, 0x00000020); +} diff --git a/src/soc/mediatek/mt8189/dptx_hal.c b/src/soc/mediatek/mt8189/dptx_hal.c new file mode 100644 index 0000000000..552f79b7cd --- /dev/null +++ b/src/soc/mediatek/mt8189/dptx_hal.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 10.28 + */ + +#include +#include +#include +#include +#include + +void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp) +{ + u32 mask = EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK | + EDP_TX_LN_VOLT_SWING_EN_MASK | EDP_TX_LN_PRE_EMPH_EN_MASK; + u32 value = EDP_TX_LN_VOLT_SWING_EN_MASK | EDP_TX_LN_PRE_EMPH_EN_MASK; + + for (int i = 0; i < dptx_hal_driving_offset_size; i++) + mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[i], value, mask); +} + +void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count) +{ + mtk_dp_phy_mask(mtk_dp, PHYD_DIG_GLB_OFFSET + 0x44, + GENMASK(4 + lane_count - 1, 4), GENMASK(7, 4)); +} + +void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp) +{ + mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_SW_RST, 0, BIT(0)); + udelay(10); + mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_SW_RST, BIT(0), BIT(0)); + + dptx_hal_reset_swing_preemphasis(mtk_dp); +} diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h index 2e24c1dde6..fc8bf3f03a 100644 --- a/src/soc/mediatek/mt8189/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h @@ -96,6 +96,7 @@ enum { IOCFG_BM1_BASE = IO_PHYS + 0x01D30000, IOCFG_BM2_BASE = IO_PHYS + 0x01D40000, IMP_IIC_WRAP_S_BASE = IO_PHYS + 0x01D74000, + EDP_PHY_BASE = IO_PHYS + 0x01E10000, IOCFG_LT0_BASE = IO_PHYS + 0x01E20000, IOCFG_LT1_BASE = IO_PHYS + 0x01E30000, MSDC0_TOP_BASE = IO_PHYS + 0x01E70000, @@ -105,7 +106,7 @@ enum { MFGCFG_BASE = IO_PHYS + 0x03FBF000, MMSYS_CONFIG_BASE = IO_PHYS + 0x04000000, DSI0_BASE = IO_PHYS + 0x04016000, - DISP_DVO0 = IO_PHYS + 0x04019000, + DISP_DVO0 = IO_PHYS + 0x04017000, IMGSYS1_BASE = IO_PHYS + 0x05020000, IMGSYS2_BASE = IO_PHYS + 0x05820000, VDEC_CORE_BASE = IO_PHYS + 0x0602F000, diff --git a/src/soc/mediatek/mt8189/include/soc/dp_intf.h b/src/soc/mediatek/mt8189/include/soc/dp_intf.h new file mode 100644 index 0000000000..11d0129267 --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/dp_intf.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8189_DP_DP_INTF_H__ +#define __SOC_MEDIATEK_MT8189_DP_DP_INTF_H__ + +#include + +#define CKSYS_CLK_CFG_16_CLR 0x118 +#define CKSYS_CLK_CFG_UPDATE 0xC + +#endif /* __SOC_MEDIATEK_MT8189_DP_DP_INTF_H__ */ diff --git a/src/soc/mediatek/mt8189/include/soc/dptx.h b/src/soc/mediatek/mt8189/include/soc/dptx.h new file mode 100644 index 0000000000..04ce124534 --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/dptx.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DPTX_H__ +#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DPTX_H__ + +#include + +#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DPTX_H__ */ diff --git a/src/soc/mediatek/mt8189/include/soc/dptx_hal.h b/src/soc/mediatek/mt8189/include/soc/dptx_hal.h new file mode 100644 index 0000000000..38c8644886 --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/dptx_hal.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8189_DP_DPTX_HAL_H__ +#define __SOC_MEDIATEK_MT8189_DP_DPTX_HAL_H__ + +#include + +#define DP_LINKRATE_RBR_VAL 0 +#define DP_LINKRATE_HBR_VAL 1 +#define DP_LINKRATE_HBR2_VAL 2 +#define DP_LINKRATE_HBR3_VAL 3 + +#define DP_PHY_DIG_GLB_STATUS_02_OFSSET 0x1488 + +#endif /* __SOC_MEDIATEK_MT8189_DP_DPTX_HAL_H__ */ diff --git a/src/soc/mediatek/mt8189/include/soc/dptx_reg.h b/src/soc/mediatek/mt8189/include/soc/dptx_reg.h new file mode 100644 index 0000000000..02366dc8d4 --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/dptx_reg.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8189_DP_DPTX_REG_H__ +#define __SOC_MEDIATEK_MT8189_DP_DPTX_REG_H__ + +#include + +#define DP_PHY_DIG_TX_CTL_0 0x1444 +#define RGS_AUX_LDO_EN_READY_MASK BIT(2) +#define DRIVING_FORCE 0x18 +#define EDP_TX_LN_PRE_EMPH_VAL_MASK GENMASK(6, 5) +#define EDP_TX_LN_PRE_EMPH_VAL_SHIFT 5 +#define EDP_TX_LN_VOLT_SWING_EN_MASK BIT(0) +#define EDP_TX_LN_PRE_EMPH_EN_MASK BIT(4) + +#endif /* __SOC_MEDIATEK_MT8189_DP_DPTX_REG_H__ */