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minor modification

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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo 2006-04-13 17:00:38 +00:00
commit d8d8fffa0e
7 changed files with 116 additions and 44 deletions
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4
src/northbridge/amd/gx2/chipsetinit.c
View file

@ -211,6 +211,7 @@ chipsetinit (void){
outb( P80_CHIPSET_INIT, 0x80);
ChipsetGeodeLinkInit();
#if 0
/* we hope NEVER to be in linuxbios when S3 resumes
if (! IsS3Resume()) */
{
@ -227,6 +228,7 @@ chipsetinit (void){
pmChipsetInit();
}
#endif
/* for later ... if 5536 set_usb_20(); */
@ -250,7 +252,7 @@ chipsetinit (void){
msr.lo &= ~0x100;
wrmsr(msrnum, msr);
/* Enable Post Primary IDE.*/
/* Enable Post Primary IDE.*/
msrnum = GLPCI_SB_CTRL;
msr = rdmsr(msrnum);
msr.lo |= GLPCI_CRTL_PPIDE_SET;

9
src/northbridge/amd/gx2/northbridge.c
View file

@ -102,10 +102,10 @@ struct msr_defaults {
/* we will assume 180e, the ssm region configuration, is left at default or set by VSM */
/* we will not set 0x180f, the DMM,yet */
{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
//{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
//{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
//{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
//{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
/* now for GLPCI routing */
/* GLIU0 */
P2D_BM(0x10000020, 0x1, 0x0, 0x0, 0xfff80),
@ -424,6 +424,7 @@ static void enable_dev(struct device *dev)
extern void cpubug(void);
printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
/* cpubug MUST be called before setup_gx2(), so we force the issue here */
northbridgeinit();
cpubug();
chipsetinit();
setup_gx2();

44
src/northbridge/amd/gx2/northbridgeinit.c
View file

@ -22,14 +22,14 @@ struct gliutable {
};
struct gliutable gliu0table[] = {
{.desc_name=MSR_GLIU0_BASE1,.desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/
{.desc_name=MSR_GLIU0_BASE2,.desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc*/
{.desc_name=MSR_GLIU0_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo*/
{.desc_name=MSR_GLIU0_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
{.desc_name=MSR_GLIU0_DMM,.desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
{.desc_name=MSR_GLIU0_SMM,.desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
{.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/
{.desc_name=MSR_GLIU0_BASE2, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc*/
{.desc_name=MSR_GLIU0_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo*/
{.desc_name=MSR_GLIU0_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
{.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
{.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
{.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
{.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
{.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
};
@ -45,17 +45,12 @@ struct gliutable gliu1table[] = {
{.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
};
struct gliutable *gliutables[] = {gliu0table, gliu1table, 0};
struct msrinit {
struct msrinit {
unsigned long msrnum;
msr_t msr;};
msr_t msr;
};
struct msrinit ClockGatingDefault [] = {
{GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}},
@ -100,11 +95,11 @@ struct msrinit GeodeLinkPriorityTable [] = {
{DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority.*/
{VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, /* VG Primary and Secondary Priority.*/
{GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, /* Graphics Priority.*/
{GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0017}}, /* GLPCI Priority + PID*/
{GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0017}}, /* GLPCI Priority + PID*/
{GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, /* GLCP Priority + PID*/
{VIP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, /* VIP PID*/
{AES_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0013}}, /* AES PID*/
{0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END*/
{0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END*/
};
/* do we have dmi or not? assume yes */
@ -124,7 +119,8 @@ writeglmsr(struct gliutable *gl){
}
static void
ShadowInit(struct gliutable *gl) {
ShadowInit(struct gliutable *gl)
{
msr_t msr;
msr = rdmsr(gl->desc_name);
@ -141,9 +137,8 @@ ShadowInit(struct gliutable *gl) {
*/
extern int sizeram(void);
static void
SysmemInit(struct gliutable *gl) {
SysmemInit(struct gliutable *gl)
{
msr_t msr;
int sizembytes, sizebytes;
@ -515,6 +510,7 @@ performance:
printk_debug("%s: MSR 0x%x will be set to 0x%x:0x%x\n", __FUNCTION__,
gating->msrnum, msr.hi, msr.lo);
wrmsr(gating->msrnum, msr);
gating +=1;
}
}
@ -534,6 +530,7 @@ GeodeLinkPriority(void){
printk_debug("%s: MSR 0x%x will be set to 0x%x:0x%x\n", __FUNCTION__,
prio->msrnum, msr.hi, msr.lo);
wrmsr(prio->msrnum, msr);
prio +=1;
}
}
@ -550,10 +547,11 @@ GeodeLinkPriority(void){
/* ***************************************************************************/
void
northbridgeinit(void){
northbridgeinit(void)
{
int i;
printk_debug("Enter %s\n", __FUNCTION__);
// post(POST_NORTHB_INIT);
for(i = 0; gliutables[i]; i++)
GLIUInit(gliutables[i]);