From d8905a7d3589e9e5a1c882c43871cd99680a63fe Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Mon, 19 Nov 2001 21:41:15 +0000 Subject: [PATCH] Digital logic smartcore-p5 --- .../digitallogic/smartcore-p5/Config | 27 +++ .../digitallogic/smartcore-p5/config.example | 20 ++ .../digitallogic/smartcore-p5/do_ramtest.inc | 5 + .../digitallogic/smartcore-p5/irq_tables.c | 163 ++++++++++++++++ .../digitallogic/smartcore-p5/mainboard.c | 183 ++++++++++++++++++ 5 files changed, 398 insertions(+) create mode 100644 src/mainboard/digitallogic/smartcore-p5/Config create mode 100644 src/mainboard/digitallogic/smartcore-p5/config.example create mode 100644 src/mainboard/digitallogic/smartcore-p5/do_ramtest.inc create mode 100644 src/mainboard/digitallogic/smartcore-p5/irq_tables.c create mode 100644 src/mainboard/digitallogic/smartcore-p5/mainboard.c diff --git a/src/mainboard/digitallogic/smartcore-p5/Config b/src/mainboard/digitallogic/smartcore-p5/Config new file mode 100644 index 0000000000..d4f18c5758 --- /dev/null +++ b/src/mainboard/digitallogic/smartcore-p5/Config @@ -0,0 +1,27 @@ +arch i386 +mainboardinit cpu/i386/entry16.inc +ldscript cpu/i386/entry16.lds +mainboardinit cpu/i386/reset16.inc +ldscript cpu/i386/reset16.lds + +mainboardinit pc80/serial.inc +mainboardinit arch/i386/lib/console.inc +northbridge intel/430tx +southbridge intel/piix4e +mainboardinit cpu/p6/earlymtrr.inc + +#superio SMC/fdc37c669 + +option ENABLE_FIXED_AND_VARIABLE_MTRRS +option PIIX4_DEVFN=0x38 +option NO_KEYBOARD +option ZKERNEL_START=0xfffc0000 +option ZKERNEL_MASK=0x7f +option L430TX +option SMC_BASE=0x3F0 + +object mainboard.o + +cpu p6 +cpu p5 + diff --git a/src/mainboard/digitallogic/smartcore-p5/config.example b/src/mainboard/digitallogic/smartcore-p5/config.example new file mode 100644 index 0000000000..696eeb42bf --- /dev/null +++ b/src/mainboard/digitallogic/smartcore-p5/config.example @@ -0,0 +1,20 @@ +# Sample config file for digital logic smartcore-p5 + +target smartcore-p5 + +mainboard digitallogic/smartcore-p5 + +# Enable Serial Console for debugging +option SERIAL_CONSOLE=1 +option NO_KEYBOARD + +option INBUF_COPY +option DEFAULT_CONSOLE_LOGLEVEL=9 +option DEBUG +option USE_GENERIC_ROM=1 + +# Path to your kernel (vmlinux) +linux ~/src/bios/linux-2.4.7-sis + +# Kernel command line parameters +commandline root=/dev/hda6 console=ttyS0,115200 FS_MODE=ro hda=flash hdb=flash diff --git a/src/mainboard/digitallogic/smartcore-p5/do_ramtest.inc b/src/mainboard/digitallogic/smartcore-p5/do_ramtest.inc new file mode 100644 index 0000000000..e22381e142 --- /dev/null +++ b/src/mainboard/digitallogic/smartcore-p5/do_ramtest.inc @@ -0,0 +1,5 @@ + mov $0x00000000, %eax + mov $0x0009ffff, %ebx + mov $16, %ecx + + CALLSP(ramtest) diff --git a/src/mainboard/digitallogic/smartcore-p5/irq_tables.c b/src/mainboard/digitallogic/smartcore-p5/irq_tables.c new file mode 100644 index 0000000000..82a4a3b5b5 --- /dev/null +++ b/src/mainboard/digitallogic/smartcore-p5/irq_tables.c @@ -0,0 +1,163 @@ +#include +#include + +/* + * This table must be located between 0x000f0000 and 0x000fffff. + * By defining it as a const it gets located in the code segment + * and therefore inside the necessary 64K block. -tds + */ + +#define USB_DEVFN (PIIX4_DEVFN+2) +#define SUM_REST 0x00 /* ...just happens to be 0 */ +#define CHECKSUM (0x00-(SUM_REST+PIIX4_DEVFN+USB_DEVFN)) + +// In spite of the comment below I have located this in the +// gigabit tree until we work this all out -- RGM +/* + * This table should work for most systems using the PIIX4 + * southbridge that have 4 PCI slots. + * + * I recall that the 440GX board that Ron was using had + * the PIIX4 at a different location. This will effect the + * devfn of the router and USB controller as well as the + * checksum. Hopefully the defines will allow this to + * be a bit more portable. + * -tds + */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*5, /* u16 size - size of entire table struct */ + 0, /* u8 rtr_bus - router bus */ + PIIX4_DEVFN, /* u8 rtr_devfn - router devfn */ + 0x0e00, /* u16 exclusive_irqs - mask of IRQs for PCI use */ + 0x8086, /* u16 rtr_vendor - router vendor id */ + 0x7110, /* u16 rtr_devfn - router device id */ + 0, /* u8 miniport_data - "crap" */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + CHECKSUM, /* u8 checksum - mod 256 checksum must give zero */ + /* struct irq_info slots[0] */ + { + { + 0, /* u8 bus */ + USB_DEVFN, /* u8 devfn for USB controller */ + { + { + 0x00, /* u8 link - IRQ line ID */ + 0x0000, /* u16 bitmap - Available IRQs */ + }, + { + 0x00, /* u8 link - IRQ line ID */ + 0x0000, /* u16 bitmap - Available IRQs */ + }, + { + 0x00, /* u8 link - IRQ line ID */ + 0x0000, /* u16 bitmap - Available IRQs */ + }, + { + 0x63, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + } + }, + 0, /* u8 slot */ + 0, /* u8 rfu */ + }, + { + 0, /* u8 bus */ + 0x40, /* u8 devfn for PCI slot 1 */ + { + { + 0x60, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x61, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x62, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x63, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + } + }, + 1, /* u8 slot */ + 0, /* u8 rfu */ + }, + { + 0, /* u8 bus */ + 0x48, /* u8 devfn for PCI slot 2 */ + { + { + 0x61, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x62, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x63, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x60, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + } + }, + 2, /* u8 slot */ + 0, /* u8 rfu */ + }, + { + 0, /* u8 bus */ + 0x50, /* u8 devfn for PCI slot 3 */ + { + { + 0x62, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x63, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x60, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x61, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + } + }, + 3, /* u8 slot */ + 0, /* u8 rfu */ + }, + { + 0, /* u8 bus */ + 0x58, /* u8 devfn for PCI slot 4 */ + { + { + 0x63, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x60, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x61, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x62, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + } + }, + 4, /* u8 slot */ + 0, /* u8 rfu */ + } + } +}; diff --git a/src/mainboard/digitallogic/smartcore-p5/mainboard.c b/src/mainboard/digitallogic/smartcore-p5/mainboard.c new file mode 100644 index 0000000000..2d393d97a0 --- /dev/null +++ b/src/mainboard/digitallogic/smartcore-p5/mainboard.c @@ -0,0 +1,183 @@ +#include +#include + +#include + +// this needs to be moved about a bit to northbridge.c etc. + + +void mainboard_fixup() +{ + struct pci_dev *pm_pcidev; + // struct pci_dev *host_bridge_pcidev; + struct pci_dev *nic_pcidev; + unsigned smbus_io, pm_io; + unsigned int i, j; + printk_debug("intel_mainboard_fixup()\n"); + +#if 1 + pm_pcidev = pci_find_device(0x8086, 0x7113, 0); + nic_pcidev = pci_find_device(0x8086, 0x1229, 0); + // host_bridge_pcidev = pci_find_slot(0, PCI_DEVFN(0,0)); +#endif +#if 1 + pci_write_config_byte(nic_pcidev, 0x3c, 21); +#endif +#if 0 + { + u8 byte; + u16 word; + u32 dword; + for(i = 0; i < 8; i++) { + pci_read_config_byte(host_bridge_pcidev, 0x60 +i, &byte); + printk_debug("DRB[i] = 0x%02x\n", byte); + } + pci_read_config_byte(host_bridge_pcidev, 0x57, &byte); + printk_debug("DRAMC = 0x%02x\n", byte); + pci_read_config_byte(host_bridge_pcidev, 0x74, &byte); + printk_debug("RPS = 0x%02x\n", byte); + pci_read_config_word(host_bridge_pcidev, 0x78, &word); + printk_debug("PGPOL = 0x%04x\n", word); + pci_read_config_dword(host_bridge_pcidev, 0x50, &dword); + printk_debug("NBXCFG = 0x%04x\n", dword); + } + +#endif +#if 0 + + printk_debug("Reset Control Register\n"); + outb(((inb(0xcf9) & 0x04) | 0x02), 0xcf9); + + printk_debug("port 92\n"); + outb((inb(0x92) & 0xFE), 0x92); + + printk_debug("Disable Nmi\n"); + outb(0, 0x70); + + printk_debug("enabling smbus\n"); +#if 0 + smbus_io = NewPciIo(0x10); +#else + smbus_io = 0xFFF0; +#endif + pci_write_config_dword(pm_pcidev, 0x90, smbus_io | 1); /* iobase addr */ + pci_write_config_byte(pm_pcidev, 0xd2, (0x4 << 1) | 1); /* smbus enable */ + pci_write_config_word(pm_pcidev, 0x4, 1); /* iospace enable */ + + + printk_debug("enable pm functions\n"); +#if 0 + pm_io = NewPciIo(0x40); +#else + pm_io = 0xFF80; +#endif + pci_write_config_dword(pm_pcidev, 0x40, pm_io | 1); /* iobase addr */ + pci_write_config_byte(pm_pcidev, 0x80, 1); /* enable pm io address */ + + printk_debug("disabling smi\n"); + /* GLBEN */ + outw(0x00, pm_io + 0x20); + /* GLBCTL */ + outl((1 << 24), pm_io + 0x28); + + printk_debug("Disable more pm stuff\n"); + /* PMEN */ + outw((1 << 8), pm_io + 0x02); + /* PMCNTRL */ + outw((0x5 << 10) , pm_io + 0x4); + /* PMTMR */ + outl(0, pm_io + 0x08); + /* GPEN */ + outw(0, pm_io + 0x0e); + /* PCNTRL */ + outl(0, pm_io + 0x10); + /* GLBSTS */ + /* DEVSTS */ + /* GLBEN see above */ + /* GLBCTL see above */ + /* DEVCTL */ + outl(0, pm_io + 0x2c); + /* GPIREG */ + /* GPOREG */ + + printk_debug("Set the subsystem vendor id\n"); + pci_write_config_word(host_bridge_pcidev, 0x2c, 0x8086); + + printk_debug("Disabling pm stuff in pci config space\n"); + +#define MAX_COUNTERS +#ifndef MAX_COUNTERS + /* counters to 0 */ +#define WHICH_COUNTERS(min,max) min +#else + /* max out the counters */ +#define WHICH_COUNTERS(min,max) max +#endif + + /* CNTA */ + pci_write_config_dword(pm_pcidev, 0x44, WHICH_COUNTERS(0x004000f0, 0xFFFFFFFF)); + + /* CNTB */ + pci_write_config_dword(pm_pcidev, 0x48, WHICH_COUNTERS(0x00000400, 0x007c07df)); + + /* GPICTL */ + pci_write_config_dword(pm_pcidev, 0x4c, 0); + + /* DEVRESD */ + pci_write_config_dword(pm_pcidev, 0x50, 0); + + /* DEVACTA */ + pci_write_config_dword(pm_pcidev, 0x54, 0); + + /* DEVACTB */ + pci_write_config_dword(pm_pcidev, 0x58, 0); + + /* DEVRESA */ + pci_write_config_dword(pm_pcidev, 0x5c, 0); + + /* DEVRESB */ + pci_write_config_dword(pm_pcidev, 0x60, 0); + + /* DEVRESC */ + pci_write_config_dword(pm_pcidev, 0x64, 0); /* might kill the serial port */ + + /* DEVRESE */ + pci_write_config_dword(pm_pcidev, 0x68, 0); + + /* DEVRESF */ + pci_write_config_dword(pm_pcidev, 0x6c, 0); + + /* DEVRESG */ + pci_write_config_dword(pm_pcidev, 0x70, 0); + + /* DEVRESH */ + pci_write_config_dword(pm_pcidev, 0x74, 0); + + /* DEVRESI */ + pci_write_config_dword(pm_pcidev, 0x78, 0); + + /* DEVRESJ */ + pci_write_config_dword(pm_pcidev, 0x7c, 0); + +#endif + +#if 1 + + /* Verify that smi is disabled */ + printk_debug("Testing SMI\r\n"); + { + u32 value; + pci_read_config_dword(pm_pcidev, 0x58, &value); + pci_write_config_dword(pm_pcidev, 0x58, value | (1 << 25)); + } + outb(inb(0xb2), 0xb2); + printk_debug("SMI disabled\r\n"); +#endif +#if 0 + + for(i = 0; i < 255; i++) { + printk_debug("%08x\r\n", i); + __rdtsc_delay2(1000000000UL, pm_io); + } +#endif +}