From d8064519511186180d0eb43217ca640b152c1c65 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 9 Jan 2017 14:19:37 -0600 Subject: [PATCH] UPSTREAM: amd/mct/ddr3: Correctly program maximum read latency The existing code inadvertently calculated the maximum read latency for nonexistent channel 2 instead of for channels 0 and 1 as intended. Fix the calls to the maximum read latency training function. BUG=none BRANCH=none TEST=none Change-Id: I020e2cf73a59d31d83ce63392f39419e714f0fd6 Signed-off-by: Patrick Georgi Original-Commit-Id: 8fa624784e3d78e67cf7b4e0e72cb2208c399f0f Original-Found-by: Coverity Scan #1347354 Original-Change-Id: If34b204ac73cd20859102cc3b2f40bc99c2ce471 Original-Signed-off-by: Timothy Pearson Original-Reviewed-on: https://review.coreboot.org/18072 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Martin Roth Original-Reviewed-by: Paul Menzel Original-Tested-by: Raptor Engineering Automated Test Stand Reviewed-on: https://chromium-review.googlesource.com/428244 Commit-Ready: Aaron Durbin --- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index fd8a8e76af..984f604135 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -1484,8 +1484,9 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, } } - /* Calculate and program MaxRdLatency */ - Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, Channel, 0); + /* Calculate and program MaxRdLatency for both channels */ + Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, 0, 0); + Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, 1, 0); if (_DisableDramECC) { mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC);