From d7ea9febdf2c5942f81607ee6ded786c9a8954bb Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 7 Apr 2014 01:01:56 -0700 Subject: [PATCH] tegra: spi: Read the command1 register to ensure the write to it completes. To ensure that the command1 write which sets the "go" bit completes before other reads to the device. Otherwise, there's a race condition where those register values might still have their values from the last transfer. With different SPI clock frequencies, that could lead to spi_delay being told there were negative bytes still to send. Its expected delay would wrap to a negative value, that was passed to udelay, and the system would sit there for 4 seconds not doing anything. BUG=None TEST=Built and booted on nyan. Set the SPI bus frequency to a value which was causing the 4+ second delay and verified that it no longer happened. BRANCH=None Change-Id: I8b4090efc69f34d0413e3f63c59c1825dd151cec Signed-off-by: Gabe Black Reviewed-on: https://chromium-review.googlesource.com/193347 Reviewed-by: Gabe Black Commit-Queue: Gabe Black Tested-by: Gabe Black --- src/soc/nvidia/tegra124/spi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 6e97a76d6d..77f017d0fd 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -402,6 +402,8 @@ static void tegra_spi_pio_start(struct tegra_spi_channel *spi) { setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); setbits_le32(&spi->regs->command1, SPI_CMD1_GO); + /* Make sure the write to command1 completes. */ + read32(&spi->regs->command1); } static inline u32 rx_fifo_count(struct tegra_spi_channel *spi)