From d7dfe4c2c289c837c0b76030815d7cd5dca0404c Mon Sep 17 00:00:00 2001
From: Aaron Durbin <adurbin@chromium.org>
Date: Wed, 23 Jul 2014 16:17:50 -0500
Subject: [PATCH] t132: prepare for ramstage vboot verification

Implement the necesary logic for running vboot
verification on ramstage. The logic just handles
the fallback path of loading from cbfs.

BUG=chrome-os-partner:30784
BRANCH=None
TEST=Built for rush.

Change-Id: I7b4fa0438efbdb0af7420e1a8b87f4fa4a86c0ee
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/209571
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
---
 src/soc/nvidia/tegra132/romstage.c | 28 ++++++++++++++++++++++++++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
index 9d1a034cea..7514fb3a80 100644
--- a/src/soc/nvidia/tegra132/romstage.c
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -22,6 +22,7 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <arch/exception.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #include <soc/addressmap.h>
 #include <soc/sdram_configs.h>
@@ -31,6 +32,25 @@
 #include <soc/clock.h>
 
 void romstage(void);
+
+static void *load_ramstage(void)
+{
+	void *entry;
+
+	/*
+	 * This platform does not need to cache a loaded ramstage nor do we
+	 * go down this path on resume. Therefore, no romstage_handoff is
+	 * required.
+	 */
+	entry = vboot_verify_firmware_get_entry(NULL);
+
+	if (entry == NULL)
+		entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
+					CONFIG_CBFS_PREFIX "/ramstage");
+
+	return entry;
+}
+
 void romstage(void)
 {
 	void *entry;
@@ -65,8 +85,12 @@ void romstage(void)
 	ccplex_load_mts();
 	printk(BIOS_INFO, "T132 romstage: MTS loading done\n");
 
-	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
-				CONFIG_CBFS_PREFIX "/ramstage");
+	entry = load_ramstage();
+
+	if (entry == NULL) {
+		printk(BIOS_INFO, "T132 romstage: error loading ramstage\n");
+		clock_halt_avp();
+	}
 
 	cbmemc_reinit();