From d79ba5565d7235935e166a23957f2e32eb131b78 Mon Sep 17 00:00:00 2001 From: Kun Liu Date: Tue, 17 Dec 2024 15:33:16 +0800 Subject: [PATCH] mb/google/nissa/var/telith: Modify PLD for typeC and typeA Modify PLD according to the actual positions of typeC and typeA on the DUT. +----------------+ | | | Screen | | | +----------------+ C0 | | A0 | | C1 | | +----------------+ BUG=b:372506691 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ifc5cd7c8e61b20632d2dcf4b7b2d506c42162063 Signed-off-by: Kun Liu Reviewed-on: https://review.coreboot.org/c/coreboot/+/85618 Reviewed-by: Rui Zhou Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Subrata Banik --- .../google/brya/variants/telith/overridetree.cb | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/brya/variants/telith/overridetree.cb b/src/mainboard/google/brya/variants/telith/overridetree.cb index 4f1b16e5c0..b48d8a657f 100644 --- a/src/mainboard/google/brya/variants/telith/overridetree.cb +++ b/src/mainboard/google/brya/variants/telith/overridetree.cb @@ -348,11 +348,11 @@ chip soc/intel/alderlake # TCP0 (DP-1) for port C0 register "device[2].name" = ""DD02"" register "device[2].use_pld" = "true" - register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" # TCP1 (DP-2) for port C1 register "device[3].name" = ""DD03"" register "device[3].use_pld" = "true" - register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" device generic 0 on end end end @@ -570,10 +570,10 @@ chip soc/intel/alderlake device ref tcss_usb3_port2 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "desc" = ""USB3 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port1 on end end end @@ -598,17 +598,17 @@ chip soc/intel/alderlake device ref usb2_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "desc" = ""USB2 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(3, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -637,7 +637,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(3, 1))" device ref usb3_port1 on end end chip drivers/usb/acpi