Some more DIMM0 related cleanups and deduplication.
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do. - spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of romstage.c files and lots of spd_addr.h files. Don't even bother for those spd_addr.h which aren't even actually used, drop them right away. - Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1, and 0xa0 with (DIMM0 << 1) where appropriate. - Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0, SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC. - VIA VX800: Drop unused SMBUS_ADDR_CH* #defines. - VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do. Then, replace 0xa0 (which now becomes 0x50) with DIMM0. - alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes. - Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
9bd9a90d6a
commit
d773fd370a
56 changed files with 250 additions and 1511 deletions
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@ -86,11 +86,6 @@ static int spd_read_byte(u32 device, u32 address)
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#include "northbridge/amd/amdfam10/early_ht.c"
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#include "southbridge/amd/sb700/sb700_early_setup.c"
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//#include "spd_addr.h"
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#define RC00 0
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#define RC01 1
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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@ -1,194 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/**
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* This file defines the SPD addresses for the mainboard. Must be included in
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* romstage.c
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*/
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#define RC00 0
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#define RC01 1
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#define RC02 2
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#define RC03 3
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#define RC04 4
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#define RC05 5
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#define RC06 6
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#define RC07 7
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#define RC08 8
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#define RC09 9
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#define RC10 10
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#define RC11 11
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#define RC12 12
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#define RC13 13
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#define RC14 14
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#define RC15 15
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#define RC16 16
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#define RC17 17
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#define RC18 18
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#define RC19 19
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#define RC20 20
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#define RC21 21
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#define RC22 22
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#define RC23 23
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#define RC24 24
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#define RC25 25
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#define RC26 26
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#define RC27 27
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#define RC28 28
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#define RC29 29
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#define RC30 30
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#define RC31 31
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#define RC32 32
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#define RC33 33
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#define RC34 34
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#define RC35 35
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#define RC36 36
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#define RC37 37
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#define RC38 38
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#define RC39 39
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#define RC40 40
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#define RC41 41
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#define RC42 42
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#define RC43 43
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#define RC44 44
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#define RC45 45
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#define RC46 46
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#define RC47 47
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#define RC48 48
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#define RC49 49
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#define RC50 50
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#define RC51 51
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#define RC52 52
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#define RC53 53
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#define RC54 54
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#define RC55 55
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#define RC56 56
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#define RC57 57
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#define RC58 58
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#define RC59 59
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#define RC60 60
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#define RC61 61
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#define RC62 62
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#define RC63 63
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#define DIMM0 0x50
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#define DIMM1 0x51
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#define DIMM2 0x52
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#define DIMM3 0x53
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#define DIMM4 0x54
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#define DIMM5 0x55
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#define DIMM6 0x56
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#define DIMM7 0x57
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static const u8 spd_addr[] = {
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//first node
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RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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#if CONFIG_MAX_PHYSICAL_CPUS > 1
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//second node
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RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
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#endif
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#if CONFIG_MAX_PHYSICAL_CPUS > 2
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// third node
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RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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// forth node
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RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
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#endif
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#if CONFIG_MAX_PHYSICAL_CPUS > 4
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RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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#endif
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#if CONFIG_MAX_PHYSICAL_CPUS > 6
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RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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#endif
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#if CONFIG_MAX_PHYSICAL_CPUS > 8
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RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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#endif
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#if CONFIG_MAX_PHYSICAL_CPUS > 12
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RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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#endif
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#if CONFIG_MAX_PHYSICAL_CPUS > 16
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RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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#endif
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#if CONFIG_MAX_PHYSICAL_CPUS > 20
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RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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#endif
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#if CONFIG_MAX_PHYSICAL_CPUS > 24
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RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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#endif
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#if CONFIG_MAX_PHYSICAL_CPUS > 32
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RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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#endif
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#if CONFIG_MAX_PHYSICAL_CPUS > 48
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RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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#endif
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};
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@ -17,87 +17,9 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/**
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* This file defines the SPD addresses for the mainboard. Must be included in
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* romstage.c
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*/
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#define RC00 0
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#define RC01 1
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#define RC02 2
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#define RC03 3
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#define RC04 4
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#define RC05 5
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#define RC06 6
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#define RC07 7
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#define RC08 8
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#define RC09 9
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#define RC10 10
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#define RC11 11
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#define RC12 12
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#define RC13 13
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#define RC14 14
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#define RC15 15
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#define RC16 16
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#define RC17 17
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#define RC18 18
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#define RC19 19
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#define RC20 20
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#define RC21 21
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#define RC22 22
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#define RC23 23
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#define RC24 24
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#define RC25 25
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#define RC26 26
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#define RC27 27
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#define RC28 28
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#define RC29 29
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#define RC30 30
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#define RC31 31
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#define RC32 32
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#define RC33 33
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#define RC34 34
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#define RC35 35
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#define RC36 36
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#define RC37 37
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#define RC38 38
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#define RC39 39
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#define RC40 40
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#define RC41 41
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#define RC42 42
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#define RC43 43
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#define RC44 44
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#define RC45 45
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#define RC46 46
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#define RC47 47
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#define RC48 48
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#define RC49 49
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#define RC50 50
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#define RC51 51
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#define RC52 52
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#define RC53 53
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#define RC54 54
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#define RC55 55
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#define RC56 56
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#define RC57 57
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#define RC58 58
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#define RC59 59
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#define RC60 60
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#define RC61 61
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#define RC62 62
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#define RC63 63
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#define DIMM0 0x50
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#define DIMM1 0x51
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#define DIMM2 0x52
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#define DIMM3 0x53
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#define DIMM4 0x54
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#define DIMM5 0x55
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#define DIMM6 0x56
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#define DIMM7 0x57
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/** This file defines the SPD addresses for the mainboard. */
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#include <spd.h>
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static const u8 spd_addr[] = {
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//first node
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@ -191,4 +113,3 @@ static const u8 spd_addr[] = {
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RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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#endif
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};
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@ -86,11 +86,6 @@ static int spd_read_byte(u32 device, u32 address)
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#include "southbridge/amd/sb700/sb700_early_setup.c"
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#include <spd.h>
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//#include "spd_addr.h"
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#define RC00 0
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#define RC01 1
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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@ -1,194 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
|
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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||||
*/
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/**
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* This file defines the SPD addresses for the mainboard. Must be included in
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* romstage.c
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*/
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#define RC00 0
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#define RC01 1
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#define RC02 2
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#define RC03 3
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#define RC04 4
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#define RC05 5
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#define RC06 6
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#define RC07 7
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#define RC08 8
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#define RC09 9
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#define RC10 10
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#define RC11 11
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#define RC12 12
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#define RC13 13
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#define RC14 14
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#define RC15 15
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#define RC16 16
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#define RC17 17
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#define RC18 18
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#define RC19 19
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#define RC20 20
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#define RC21 21
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#define RC22 22
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#define RC23 23
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#define RC24 24
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#define RC25 25
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#define RC26 26
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#define RC27 27
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#define RC28 28
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#define RC29 29
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#define RC30 30
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#define RC31 31
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#define RC32 32
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#define RC33 33
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#define RC34 34
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#define RC35 35
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#define RC36 36
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#define RC37 37
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#define RC38 38
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#define RC39 39
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#define RC40 40
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#define RC41 41
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#define RC42 42
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#define RC43 43
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#define RC44 44
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#define RC45 45
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#define RC46 46
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#define RC47 47
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#define RC48 48
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#define RC49 49
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#define RC50 50
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#define RC51 51
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#define RC52 52
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#define RC53 53
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#define RC54 54
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#define RC55 55
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#define RC56 56
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#define RC57 57
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#define RC58 58
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#define RC59 59
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#define RC60 60
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#define RC61 61
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#define RC62 62
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#define RC63 63
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|
||||
#define DIMM0 0x50
|
||||
#define DIMM1 0x51
|
||||
#define DIMM2 0x52
|
||||
#define DIMM3 0x53
|
||||
#define DIMM4 0x54
|
||||
#define DIMM5 0x55
|
||||
#define DIMM6 0x56
|
||||
#define DIMM7 0x57
|
||||
|
||||
|
||||
static const u8 spd_addr[] = {
|
||||
//first node
|
||||
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
//second node
|
||||
RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 2
|
||||
// third node
|
||||
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
// forth node
|
||||
RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 4
|
||||
RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 6
|
||||
RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 8
|
||||
RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 12
|
||||
RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 16
|
||||
RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 20
|
||||
RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 24
|
||||
RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 32
|
||||
RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 48
|
||||
RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
};
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue