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soc/intel/quark: Set the UPD values for MemoryInit

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Set the UPD values for MemoryInit.
*  Update the FspUpdVpd.h file which specifies the parameters for
   MemoryInit.
*  Add the necessary values to chip.h to enable values to come from
   the mainboard's devicetree.cb file
*  Add the parameters to the mainboard's devicetree.cb file
*  Locate the platform configuration database file (pdat.bin)
*  Copy the data values from the chip_info structure into the UPDs
*  Display the UPD values

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
   UEFIPAYLOAD.fd
*  Edit .config file and add the following lines:
   *  CONFIG_DISPLAY_UPD_DATA=y
*  Testing successful when the UPD data is displayed before the call to
   MemoryInit

Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13896
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Lee Leahy 2016-03-03 15:30:48 -08:00 • committed by Martin Roth
commit d76d60bf56
5 changed files with 149 additions and 71 deletions
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10
src/mainboard/intel/galileo/devicetree.cb
View file

@ -16,6 +16,16 @@
chip soc/intel/quark
############################################################
# Set the parameters for MemoryInit
############################################################
register "PcdSmmTsegSize" = "0" # SMM Region size in MiB
############################################################
# Enable the devices
############################################################
device domain 0 on
# EDS Table 3
device pci 00.0 on end # 8086 0958 - Host Bridge