From d7627a39e86bd17030224b62bb6b0b0dc3a04fae Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Tue, 14 Oct 2025 20:11:34 +0100 Subject: [PATCH] mb/starlabs/starbook/adl: Tidy up GPIO config straps Apply the standard format for configuring the config straps. The configuration of the straps isn't changed, just written more clearly. Change-Id: I2cf130fbf7572a4014e97c14885951e5f604cfa8 Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/89578 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- .../starlabs/starbook/variants/adl/gpio.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c index c33c57dec2..dbf0e67c38 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c @@ -82,16 +82,16 @@ const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_E8, 1, DEEP), /* DRAM Sleep */ /* Config Straps [ Low / High ] */ - PAD_NC(GPP_B14, NONE), /* Top Swap [ Disabled / Enabled ] */ - PAD_NC(GPP_B18, NONE), /* Reboot Support [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* Top Swap [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* Reboot Support [ Enabled / Disabled ] */ PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* TLS Confidentiality [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_C5, 0, DEEP), /* eSPI [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_E6, 0, DEEP), /* JTAG ODT [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_H1, 0, DEEP), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ - PAD_NC(GPP_F2, NONE), /* M.2 CNVi [ Enabled / Disabled ] */ - PAD_NC(GPP_E19, NONE), /* TBT LSX #0 [ 1.8V / 3.3V ] */ - PAD_CFG_GPO(GPP_F7, 0, DEEP), /* MCRO LDO [ Disabled / Bypass ] */ - PAD_CFG_GPO(GPD7, 0, PWROK), /* RTC Clock Delay [ Disabled / 95ms ] */ + PAD_CFG_GPO(GPP_C5, 0, PLTRST), /* eSPI [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_E6, 0, PLTRST), /* JTAG ODT [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_H1, 0, PLTRST), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_F2, 0, PLTRST), /* M.2 CNVi [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_E19, 0, PLTRST), /* TBT LSX #0 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_F7, 0, PLTRST), /* MCRO LDO [ Disabled / Bypass ] */ + PAD_CFG_GPO(GPD7, 0, PLTRST), /* RTC Clock Delay [ Disabled / 95ms ] */ PAD_NC(GPD2, NONE),