diff --git a/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h
index ad26ab8a67..d82877fe06 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h
@@ -40,4 +40,9 @@ void baseboard_devtree_update(void);
 /* Modify devictree settings during ramstage by dedicated variant */
 void variant_devtree_update(void);
 
-#endif /*__BASEBOARD_VARIANTS_H__ */
+enum variant_board_id {
+	BOARD_ID_DDR5 = 0x20,
+	BOARD_ID_LP5X = 0x21,
+};
+
+#endif /* __BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory.c b/src/mainboard/google/ocelot/variants/ocelot/memory.c
index e0908adabd..7ac5ce95fd 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory.c
@@ -1,56 +1,40 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <baseboard/variants.h>
-#include <soc/romstage.h>
+#include <boardid.h>
 #include <soc/meminit.h>
+#include <soc/romstage.h>
+
+#define BOARD_ID_MASK	0x3f
+#define SMBUS_ADDR_DIMM	0x50
 
 static const struct mb_cfg lp5_mem_config = {
 	.type = MEM_TYPE_LP5X,
 
 	.lpx_dq_map = {
 		.ddr0 = {
-			.dq0 = {  13,  14,  12,  15, 11,  10,  8,  9, },
-			.dq1 = {  7,  5,  4,  6,  0,  3,  1,  2 },
+			.dq0 = {  10,  11,  8,  9,  15,  14,  12,  13, },
+			.dq1 = {  7,  4,  5,  6,  3,  0,  2,  1 },
 		},
 		.ddr1 = {
-			.dq0 = {  1,  3,  0,  2,  7,  4,  6,  5, },
-			.dq1 = {  12,  13,  14,  15,  11,  10,  9,  8 },
+			.dq0 = {  8,  11,  10,  9,  15,  12,  13,  14, },
+			.dq1 = {  6,  7,  5,  4,  1,  3,  0,  2 },
 		},
 		.ddr2 = {
-			.dq0 = {  0,  2,  1,  3,  6,  4,  7,  5 },
-			.dq1 = {  14,  13,  15,  12,  8,  11,  10,  9, },
+			.dq0 = {  3,  2,  1,  0,  6,  7,  5,  4, },
+			.dq1 = {  9,  8,  10,  11,  15,  12,  13,  14 },
 		},
 		.ddr3 = {
-			.dq0 = {  6,  5,  7,  4,  2,  3,  1,  0, },
-			.dq1 = {  10,  8,  11,  9,  12,  15,  13,  14 },
-		},
-		.ddr4 = {
-			.dq0 = {  2,  1,  3,  0,  4,  7,  5,  6 },
-			.dq1 = {  15,  14,  12,  13,  9,  11,  10,  8, },
-		},
-		.ddr5 = {
-			.dq0 = {  6,  5,  7,  4,  3,  1,  0,  2, },
-			.dq1 = {  10,  9,  11,  8,  13,  14,  12,  15 },
-		},
-		.ddr6 = {
-			.dq0 = {  9,  10,  11,  8,  14,  12,  13, 15, },
-			.dq1 = {  0,  1,  2,  3,  5,  7,  4,  6 },
-		},
-		.ddr7 = {
-			.dq0 = {  0,  1,  2,  3,  7,  5,  6,  4, },
-			.dq1 = {  14,  13,  15,  12,  10,  8,  11,  9 },
+			.dq0 = {  8,  11,  10,  9,  15,  13,  12,  14, },
+			.dq1 = {  4,  5,  6,  7,  1,  3,  2,  0 },
 		},
 	},
 
 	.lpx_dqs_map = {
 		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
 		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+		.ddr3 = { .dqs0 = 1, .dqs1 = 0 },
 	},
 
 	.ect = true, /* Early Command Training */
@@ -64,13 +48,54 @@ static const struct mb_cfg lp5_mem_config = {
 	},
 };
 
+static const struct mb_cfg ddr5_mem_config = {
+	.type = MEM_TYPE_DDR5,
+
+	.ect = true, /* Early Command Training */
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.lp_ddr_dq_dqs_re_training = 1,
+
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	},
+};
+
 const struct mb_cfg *variant_memory_params(void)
 {
-	return &lp5_mem_config;
+	uint32_t id = board_id() & BOARD_ID_MASK;
+	printk(BIOS_INFO, "Board ID: %u\n", id);
+
+	switch (id) {
+	case BOARD_ID_DDR5:
+		return &ddr5_mem_config;
+	case BOARD_ID_LP5X:
+		return &lp5_mem_config;
+	default:
+		printk(BIOS_INFO, "Valid Board IDs: DDR5 = %u, LP5X = %u\n", BOARD_ID_DDR5, BOARD_ID_LP5X);
+		die("Unknown Board ID: %u\n", id);
+		break;
+	}
 }
 
 void variant_get_spd_info(struct mem_spd *spd_info)
 {
-	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	uint32_t id = board_id() & BOARD_ID_MASK;
 	spd_info->cbfs_index = 0;
+
+	switch (id) {
+	case BOARD_ID_DDR5:
+		spd_info->topo = MEM_TOPO_DIMM_MODULE;
+		spd_info->smbus[0].addr_dimm[0] = SMBUS_ADDR_DIMM;
+		spd_info->smbus[1].addr_dimm[0] = SMBUS_ADDR_DIMM;
+		break;
+	case BOARD_ID_LP5X:
+		spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+		break;
+	default:
+		printk(BIOS_INFO, "Valid Board IDs: DDR5 = %u, LP5X = %u\n", BOARD_ID_DDR5, BOARD_ID_LP5X);
+		die("Unknown Board ID: %u\n", id);
+		break;
+	}
 }