erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

libpayload: usb: xhci: Fix TD size if it overflows 5 bits

Browse source 
xHCI Spec says TD Size (5 bits) field shall be forced to 31,
if the number of packets to be scheduled is greater than 31.

BUG=chrome-os-partner:27837
BRANCH=rambi,nyan
TEST=Manual: Ensure recovery boot with USB 2.0 media on Squawks
works fine without any babble errors.

Original-Change-Id: Iff14000e2a0ca1b28c49d0da921dbb2a350a1bbd
Original-Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com>
Original-Originally-Reviewed-on: https://chromium-review.googlesource.com/202297
Original-Reviewed-on: https://chromium-review.googlesource.com/202330
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Tested-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit ae58b99370)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9668b947f676c109fad9297e5efde91bf7f796fd
Reviewed-on: http://review.coreboot.org/7913
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Rajmohan Mani 2014-05-30 13:06:01 -07:00 • committed by Marc Jones
commit d6fb32b461
2 changed files with 3 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
payloads/libpayload/drivers/usb/xhci.c
View file

@ -541,7 +541,7 @@ xhci_enqueue_td(transfer_ring_t *const tr, const int ep, const size_t mps,
xhci_clear_trb(trb, tr->pcs);
trb->ptr_low = virt_to_phys(cur_start);
TRB_SET(TL, trb, cur_length);
TRB_SET(TDS, trb, packets);
TRB_SET(TDS, trb, MIN(TRB_MAX_TD_SIZE, packets));
TRB_SET(CH, trb, 1);
/* Check for first, data stage TRB */

2
payloads/libpayload/drivers/usb/xhci_private.h
View file

@ -139,6 +139,8 @@ typedef volatile struct trb {
u32 control;
} trb_t;
#define TRB_MAX_TD_SIZE 0x1F /* bits 21:17 of TD Size in TRB */
#define EVENT_RING_SIZE 64
typedef struct {
trb_t *ring;