From d6ec4f108d2aa8e4809e7c9f9dd0079f68c5dbff Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 15 Aug 2025 01:12:54 +0530 Subject: [PATCH] soc/qualcomm/x1p42100: Mark additional reserved memory ranges This commit refactors the DRAM memory layout to reserve additional regions critical for platform functionality and debugging. It consolidates several CPUCP-related memory areas and adds new reservations for Ramdump and Shared Memory. - Ramdump and Shared Memory: New reserved regions, dram_ramdump and dram_smem, are added to protect memory used for crash dumps and inter-processor communication. - CPUCP Optimization: The individual NCC, CPUCP, and CPUCP-DTS regions are consolidated into a single, contiguous dram_cpucp region from 0x80A00000 to 0x815A0000. This simplifies the memory map and optimizes resource allocation. Reserving these regions is crucial to prevent other bootloader stages or the kernel from overwriting critical firmware data, which could lead to unexpected behavior or system instability. BUG=b:437948495 TEST=Able to ensure booting google/quenbi till kernel. Change-Id: I80f6d288dd054a34a1e60736c8b14f072559c1ac Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/88779 Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) --- src/soc/qualcomm/common/include/soc/symbols_common.h | 2 ++ src/soc/qualcomm/x1p42100/memlayout.ld | 5 +++-- src/soc/qualcomm/x1p42100/soc.c | 5 ++++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h index caa1e7d174..64cb7ae38b 100644 --- a/src/soc/qualcomm/common/include/soc/symbols_common.h +++ b/src/soc/qualcomm/common/include/soc/symbols_common.h @@ -31,6 +31,8 @@ DECLARE_REGION(dram_cpucp) DECLARE_REGION(dram_modem) DECLARE_REGION(dram_tz) DECLARE_REGION(dram_tz_rem) +DECLARE_REGION(dram_ramdump) +DECLARE_REGION(dram_smem) /* * DDR_SPACE (2 GB) aka `_dram`: 0x80000000 - 0x100000000 diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld index ea21c27331..0fdfca25f9 100644 --- a/src/soc/qualcomm/x1p42100/memlayout.ld +++ b/src/soc/qualcomm/x1p42100/memlayout.ld @@ -57,14 +57,15 @@ SECTIONS REGION(shrm, 0x24040000, 128K , 4K) DRAM_START(0x80000000) - REGION(dram_cpucp_dtbs, 0x81240000, 0x2000, 0x1000) - REGION(dram_cpucp, 0x81250000, 0x80000, 0x1000) + REGION(dram_cpucp, 0x80A00000, 0xBA0000, 0x1000) + REGION(dram_ramdump, 0x81A00000, 0x200000, 0x1000) REGION(dram_aop, 0x81C00000, 0xF780000, 0x1000) POSTRAM_CBFS_CACHE(0x9F800000, 16M) RAMSTAGE(0xA0800000, 16M) REGION(dram_tz, 0xD8000000, 0xD6000, 0x1000) BL31(0xD80D6000, 1M) REGION(dram_tz_rem, 0xD81D6000, 0x72EA000, 0x1000) + REGION(dram_smem, 0xFF800000, 0x800000, 0x1000) DRAM_END(0x100000000) /* diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c index fd429cc465..8066084fee 100644 --- a/src/soc/qualcomm/x1p42100/soc.c +++ b/src/soc/qualcomm/x1p42100/soc.c @@ -23,13 +23,16 @@ static void soc_read_resources(struct device *dev) for (int i = 0; i < count; i++) ram_range(dev, index++, (uintptr_t)config[i].offset, config[i].size); - reserved_ram_range(dev, index++, (uintptr_t)_dram_cpucp_dtbs, REGION_SIZE(dram_cpucp_dtbs)); reserved_ram_range(dev, index++, (uintptr_t)_dram_cpucp, REGION_SIZE(dram_cpucp)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_ramdump, REGION_SIZE(dram_ramdump)); + reserved_ram_range(dev, index++, (uintptr_t)_dram_tz, REGION_SIZE(dram_tz)); reserved_ram_range(dev, index++, (uintptr_t)_dram_tz_rem, REGION_SIZE(dram_tz_rem)); reserved_ram_range(dev, index++, (uintptr_t)_dram_aop, REGION_SIZE(dram_aop)); + + reserved_ram_range(dev, index++, (uintptr_t)_dram_smem, REGION_SIZE(dram_smem)); } static void soc_init(struct device *dev)