UPSTREAM: Move definitions of HIGH_MEMORY_SAVE

This is more of ACPI S3 resume and x86 definition than CBMEM.

Change-Id: Iffbfb2e30ab5ea0b736e5626f51c86c7452f3129
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15190
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
(cherry-picked from commit a969ed34db)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354182
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>

src/cpu/intel/haswell/romstage.c

@@ -24,6 +24,7 @@
 #include <halt.h>
 #include <lib.h>
 #include <timestamp.h>
+#include <arch/acpi.h>
 #include <arch/io.h>
 #include <arch/stages.h>
 #include <device/pci_def.h>

src/cpu/intel/model_206ax/cache_as_ram.inc

@@ -18,6 +18,7 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
 #include <cbmem.h>
+#include <arch/acpi.h>
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE