From d5fb4becd5890ad584e7488948c4ad84a192907b Mon Sep 17 00:00:00 2001 From: Tony Huang Date: Fri, 16 Jan 2026 15:18:29 +0800 Subject: [PATCH] mb/google/nissa/var/yavilla: Update DTT parameters This CL update max TDP from 6W to 7W as requested by thermal team. Increase tdp_pl1_override value from 6 W to 7 W. Increase PL1 max power value from 6 W to 7 W. The settings has been verified by thermal team. BUG=b:476292154, b:476292156 TEST=emerge-nissa coreboot chromeos-bootimage verified test result by thermal team Change-Id: Iaedfb2caec589dd5f5be5cc872e302d55fa51dd6 Signed-off-by: Tony Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/90774 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- .../google/brya/variants/yavilla/overridetree.cb | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb index 588919da54..8ed08cc0d3 100644 --- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb +++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb @@ -113,6 +113,12 @@ chip soc/intel/alderlake .configure_ext_fivr = 1, }" + register "power_limits_config[ADL_N_041_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 25, + .tdp_pl4 = 78, + }" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -202,7 +208,7 @@ chip soc/intel/alderlake register "controls.power_limits" = "{ .pl1 = { .min_power = 3000, - .max_power = 6000, + .max_power = 7000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200